ADSP-21369 Register Structural Header File

Applying the same idea about register structural header file described in Register File under General Guide, the ADSP-21369 register structural header file (ES_ADSP21369Reg.h) is given below.

/*********************************************************************************
*
* Embedded Studio (C) 2007
*
* File: ES_Def21369.h
* Desc: Analog Device ADSP-21369 register structural definition file
*
**********************************************************************************/

#ifndef __ES_ADSP21369REG_H_
#define __ES_ADSP21369REG_H_

/********************************************************************************/
/* ADSP-21369 Series Include File */
/********************************************************************************/

typedef union st_eemustat /* Enhanced Emulation Status Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :15; /* bit[31:17], reserved */
int STATIOY :1; /* bit[16], IOY Memory Breakpoint Status */
int EEMUINENS :1; /* bit[15], EEMUIN Interrupt Enable */
int OSPIDENS :1; /* bit[14], OSPID Register Enable */
int EEMUENS :1; /* bit[13], Enhanced Emulation Feature Enable */
int EEMUINFULL :1; /* bit[12], Enhanced Emulation EEMUIN Register Status */
int EEMUOUTFULL :1; /* bit[11], Enhanced Emulation EEMUOUT FIFO Status */
int EEMUOUTRDY :1; /* bit[10], Enhanced Emulation EEMUOUT Ready */
int EEMUOUTIRQEN :1; /* bit[9], Enhanced Emulation EEMUOUT Interrupt Enable */
int RSRVD1 :1; /* bit[8], reserved */
int STATIO :1; /* bit[7], I/O Address Breakpoint Hit */
int STATIA3 :1; /* bit[6], Instruction Address Breakpoint Hit */
int STATIA2 :1; /* bit[5], Instruction Address Breakpoint Hit */
int STATIA1 :1; /* bit[4], Instruction Address Breakpoint Hit */
int STATIA0 :1; /* bit[3], Instruction Address Breakpoint Hit */
int STATDA1 :1; /* bit[2], Data Memory Breakpoint Hit */
int STATDA0 :1; /* bit[1], Data Memory Breakpoint Hit */
int STATPA :1; /* bit[0], Program Memory Data Breakpoint Hit */
} BIT;
}ST_EEMUSTAT;

typedef union st_sysctl /* System Control Register (SYSCTL) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int BUSLK :1; /* bit[29], Bus Lock Request */
int FSYNC :1; /* bit[28], Force Synchronization of the Shared Memory Bus */
int PWM12_15 :1; /* bit[27], Pulse Width Modulation Select */
int PWM8_11 :1; /* bit[26], Pulse Width Modulation Select */
int PWM4_7 :1; /* bit[25], Pulse Width Modulation Select */
int PWM0_3 :1; /* bit[24], Pulse Width Modulation Select */
int EPDATA :3; /* bit[23:21], Data Pin Mode Select */
int MSEN :1; /* bit[20], Memory Select */
int TMREXPEN :1; /* bit[19], Flag Timer Expired Mode */
int IRQ2EN :1; /* bit[18], Flag2 Interrupt Mode */
int IRQ1EN :1; /* bit[17], Flag1 Interrupt Mode */
int IRQ0EN :1; /* bit[16], Flag0 Interrupt Mode */
int RSRVD1 :3; /* bit[15:13], reserved */
int IMDW3 :1; /* bit[12], Internal Memory Data Width 3 */
int IMDW2 :1; /* bit[11], Internal Memory Data Width 2 */
int IMDW1 :1; /* bit[10], Internal Memory Data Width 1 */
int IMDW0 :1; /* bit[9], Internal Memory Data Width 0 */
int RSRVD2 :1; /* bit[8], reserved */
int RBPR :1; /* bit[7], Rotating Priority Bus Arbitration */
int RSRVD3 :4; /* bit[6:3], reserved */
int IIVT :1; /* bit[2], Internal Interrupt Vector Table */
int RSRVD4 :1; /* bit[1], reserved */
int SRST :1; /* bit[0], Software Reset */
} BIT;
}ST_SYSCTL;

typedef union st_brkctl /* Hardware Breakpoint Control Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int ENBIOX :1; /* bit[27], IOX Breakpoint Enable */
int ENBIOY :1; /* bit[26], IOY Breakpoint Enable */
int UMODE :1; /* bit[25], User Mode Breakpoint Functionality Enable */
int ANDBKP :1; /* bit[24], AND Composite Breakpoints */
int ENBEP :1; /* bit[23], Enable External Port Address Breakpoint */
int RSRVD1 :1; /* bit[22], reserved */
int ENBIA :1; /* bit[21], Enable Instruction Address Breakpoints */
int ENBDA :1; /* bit[20], Enable Data Memory Address Breakpoints */
int ENBPA :1; /* bit[19], Enable Program Memory Data Address Breakpoints */
int NEGEP1 :1; /* bit[18], Negate EP Address Breakpoint */
int NEGIO1 :1; /* bit[17], Negate I/O Address Breakpoint */
int NEGIA4 :1; /* bit[16], Negate Instruction Address Breakpoint #4 */
int NEGIA3 :1; /* bit[15], Negate Instruction Address Breakpoint #3 */
int NEGIA2 :1; /* bit[14], Negate Instruction Address Breakpoint #2 */
int NEGIA1 :1; /* bit[13], Negate Instruction Address Breakpoint #1 */
int NEGDA2 :1; /* bit[12], Negate Data Memory Address Breakpoint #2 */
int NEGDA1 :1; /* bit[11], Negate Data Memory Address Breakpoint #1 */
int NEGPA1 :1; /* bit[10], Negate Program Memory Data Address Breakpoint */
int EP1MODE :2; /* bit[9:8], EP1 Triggering Mode */
int IO1MODE :2; /* bit[7:6], IO1 Triggering Mode */
int DA2MODE :2; /* bit[5:4], DA2 Triggering Mode */
int DA1MODE :2; /* bit[3:2], DA1 Triggering Mode */
int PA1MODE :2; /* bit[1:0], PA1Triggering Mode */
} BIT;
}ST_BRKCTL;

// IOP registers for SDRAM controller

typedef union st_sdctl /* SDRAM Control Register (SDCTL) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int NO_BSTOP :1; /* bit[31], No Burst Mode */
int PGSZ128 :1; /* bit[30], Program the SDRAM Controller for Page Size of 128 Words */
int SDRAW :3; /* bit[29:27], Row Address Width */
int SDTRCD :3; /* bit[26:24], SDRAM tRCD Specification */
int SDBUF :1; /* bit[23], Pipeline Option with External Register Buffer */
int FORCE_LMR :1; /* bit[22], Force Load Mode Register Write */
int FORCE_PC :1; /* bit[21], Force Precharge */
int FORCE_AR :1; /* bit[20], Force Auto Refresh */
int SDORF :1; /* bit[19], Optional Refresh */
int SDTWR :2; /* bit[18:17], SDRAM tWR Specification */
int X16DE :1; /* bit[16], SDRAM External Data Path Width */
int SDSRF :1; /* bit[15], Self Refresh Enable */
int SDPSS :1; /* bit[14], SDRAM Power-Up Sequence Start */
int SDCAW :2; /* bit[13:12], SDRAM Bank Column Address Width */
int SDPM :1; /* bit[11], SDRAM Power-Up Mode */
int SDTRP :3; /* bit[10:8], tRP Specification */
int SDTRAS :4; /* bit[7:4], tRAS Specification */
int DSDCLK1 :1; /* bit[3], Disable SDRAM Clock 1 */
int DSDCTL :1; /* bit[2], Disable SDCLK and Control Signals */
int SDCL :2; /* bit[1:0], SDRAM CAS Latency */
} BIT;
}ST_SDCTL;

typedef union st_epctl /* External Port Control Register (EPCTL) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :13; /* bit[31:19], reserved */
int DATE :4; /* bit[18:15], Data Enable */
int FRZCR :2; /* bit[14:13], Arbitration Freezing Length for CORE Accesses */
int RSRVD1 :2; /* bit[12:11], reserved */
int FRZDMA :2; /* bit[10:9], Arbitration Freezing Length for DMA */
int RSRVD2 :1; /* bit[8], reserved */
int DMAPR :2; /* bit[7:6], DMA Channel Priority for CH0 and CH1 */
int EPBR :2; /* bit[5:4], External Port Bus Priority */
int B3SD :1; /* bit[3], Select Bank 3 SDRAM */
int B2SD :1; /* bit[2], Select Bank 2 SDRAM */
int B1SD :1; /* bit[1], Select Bank 1 SDRAM */
int B0SD :1; /* bit[0], Select Bank 0 SDRAM */
} BIT;
}ST_EPCTL;

// IOP registers for SDRAM controller

typedef union st_sdrrc /* SDRAM Refresh Rate Control Register (SDRRC) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :11; /* bit[31:21], reserved */
int SDMODIFY :4; /* bit[20:17], Used for Predictive Addressing (0-15) */
int SDROPT :1; /* bit[16], SDRAM Optimization */
int RSRVD1 :4; /* bit[15:12], reserved */
int RDIV :12; /* bit[11:0], Delay (SDCLK cycles) between consecutive refresh counter time-outs */
} BIT;
}ST_SDRRC;

typedef union st_sdstat /* SDRAM Control Status Register (SDSTAT) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int SDRS :1; /* bit[3], SDRAMs In Reset State */
int SDPUA :1; /* bit[2], SDRAM Optimization */
int SDSRA :1; /* bit[1], SDRAM Self-Refresh Active */
int SDCI :1; /* bit[0], SDRAM Controller Idle */
} BIT;
}ST_SDSTAT;

typedef union st_systat /* System Status Register (SYSTAT) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :21; /* bit[31:11], reserved */
int IDC :3; /* bit[10:8], ID Code */
int RSRVD1 :1; /* bit[7], reserved */
int CRBM :3; /* bit[6:4], Current Bus Master */
int RSRVD2 :3; /* bit[3:1], reserved */
int BSYN :1; /* bit[0], Bus Synchronized */
} BIT;
}ST_SYSTAT;

typedef union st_amictl /* AMI Control Registers (AMICTLx) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :10; /* bit[31:22], reserved */
int NO_OPT :1; /* bit[21], Disable Predictive Reads */
int RHC :3; /* bit[20:18], Read Hold Cycle at the End of Read Access */
int FLSH :1; /* bit[17], AMI Buffer Flush (Write-only) */
int IC :3; /* bit[16:14], Bus Idle Cycle */
int HC :3; /* bit[13:11], Bus Hold Cycle at the End of Write Access */
int WS :5; /* bit[10:6], Wait States */
int ACKEN :1; /* bit[5], Enable the ACK pin */
int MSWF :1; /* bit[4], Most Significant Word First */
int PKDIS :1; /* bit[3], Disable Packing/Unpacking */
int BW :2; /* bit[2:1], External Data Bus Width */
int AMIEN :1; /* bit[0], AMI Enable */
} BIT;
}ST_AMICTL;

typedef union st_amistat /* AMI Status Register (AMISTAT) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int AMIRXS :1; /* bit[3], AMI External Receive Register (AMIRX) Status */
int AMITXS :1; /* bit[2], AMI External Transmit Register (AMITX) Status */
int AMIS :1; /* bit[1], External Interface Status */
int AMIMS :1; /* bit[0], AMI Master */
} BIT;
}ST_AMISTAT;

//DMA address registers

typedef union st_dmac /* External Port DMA Control Registers (DMACx) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :15; /* bit[31:17], reserved */
int DIRS :1; /* bit[16], DMA Transfer Direction Status (read-only) */
int EXTS :1; /* bit[15], DMA External Interface Status (read-only) */
int WBS :1; /* bit[14], Delay Line Write Pointer Write Back Status (read-only) */
int TLS :1; /* bit[13], Tap List Loading Status (read-only) */
int CHS :1; /* bit[12], DMA Chaining Status (read-only) */
int DMAS :1; /* bit[11], DMA Transfer Status (read-only) */
int TFS :2; /* bit[10:9], Tap List FIFO Status (read-only) */
int DFS :2; /* bit[8:7], DMA FIFO Status (read-only) */
int TFLSH :1; /* bit[6], Flush Tap List FIFO (write-only) */
int DFLSH :1; /* bit[5], Flush DMA FIFO (write-only) */
int CBEN :1; /* bit[4], Circular Buffering Enable */
int DLEN :1; /* bit[3], Enable Delay Line DMA */
int CHEN :1; /* bit[2], Enable Chaining */
int DMADR :1; /* bit[1], DMA Direction */
int DMAEN :1; /* bit[0], DMA Enable */
} BIT;
}ST_DMAC;

// Serial Port registers (SP01)

typedef union st_sperrstat /* SPORT Error Status Register (SPERRSTAT) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :8; /* bit[31:24], reserved */
int FSERR7 :1; /* bit[23], SP7 FSERR Int Status */
int FSERR6 :1; /* bit[22], SP6 FSERR Int Status */
int FSERR5 :1; /* bit[21], SP5 FSERR Int Status */
int FSERR4 :1; /* bit[20], SP4 FSERR Int Status */
int FSERR3 :1; /* bit[19], SP3 FSERR Int Status */
int FSERR2 :1; /* bit[18], SP2 FSERR Int Status */
int FSERR1 :1; /* bit[17], SP1 FSERR Int Status */
int FSERR0 :1; /* bit[16], SP0 FSERR Int Status */
int DERRB7 :1; /* bit[15], SP7 DERRB Int Status */
int DERRA7 :1; /* bit[14], SP7 DERRA Int Status */
int DERRB6 :1; /* bit[13], SP6 DERRB Int Status */
int DERRA6 :1; /* bit[12], SP6 DERRA Int Status */
int DERRB5 :1; /* bit[11], SP5 DERRB Int Status */
int DERRA5 :1; /* bit[10], SP5 DERRA Int Status */
int DERRB4 :1; /* bit[9], SP4 DERRB Int Status */
int DERRA4 :1; /* bit[8], SP4 DERRA Int Status */
int DERRB3 :1; /* bit[7], SP3 DERRB Int Status */
int DERRA3 :1; /* bit[6], SP3 DERRA Int Status */
int DERRB2 :1; /* bit[5], SP2 DERRB Int Status */
int DERRA2 :1; /* bit[4], SP2 DERRA Int Status */
int DERRB1 :1; /* bit[3], SP1 DERRB Int Status */
int DERRA1 :1; /* bit[2], SP1 DERRA Int Status */
int DERRB0 :1; /* bit[1], SP0 DERRB Int Status */
int DERRA0 :1; /* bit[0], SP0 DERRA Int Status */
} BIT;
}ST_SPERRSTAT;

typedef union st_spctl /* SPORT Serial Control Registers (SPCTLx) */
{
union
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int DXS_A :2; /* bit[31:30], Data Buffer Channel A Status (read-only) */
int DERR_A :1; /* bit[29], Channel A Error Status (sticky, read-only) */
int DXS_B :2; /* bit[28:27], Data Buffer Channel B Status */
int DERR_B :1; /* bit[26], Channel B Error Status (sticky) */
int SPTRAN :1; /* bit[25], SPORT Data Direction */
int SPEN_B :1; /* bit[24], SPORT Data Direction */
int BHD :1; /* bit[23], Buffer Hang Disable */
int FS_BOTH :1; /* bit[22], Frame Sync Both */
int SCHEN_B :1; /* bit[21], DMA Channel B */
int SDEN_B :1; /* bit[20], DMA Channel B Enable */
int SCHEN_A :1; /* bit[19], DMA Channel A */
int SDEN_A :1; /* bit[18], DMA Channel A Enable */
int LAFS :1; /* bit[17], Late Frame Sync */
int LFS :1; /* bit[16], Active Low Frame Sync */
int DIFS :1; /* bit[15], Data Independent TX FS (if SPTRAN=1) or RX FS (if SPTRAN=0) */
int IFS :1; /* bit[14], Internally-Generated FS */
int FSR :1; /* bit[13], Frame Sync Requirement */
int CKRE :1; /* bit[12], Clock Edge for Data Frame Sync */
int OP_MODE :1; /* bit[11], SPORT Operation Mode */
int ICLK :1; /* bit[10], Internally-Generated SPORTx_CLK */
int PACK :1; /* bit[9], 16/32 Packing */
int SLEN :5; /* bit[8:4], Serial Word Length=1 */
int LSBF :1; /* bit[3], Least Significant Bit Format */
int DTYPE :2; /* bit[2:1], Data Type */
int SPEN_A :1; /* bit[0], SPORT Enable A */
} BIT;
} STANDARD_MODE;

union
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int DXS_A :2; /* bit[31:30], Data Buffer Channel A Status (read-only) */
int DERR_A :1; /* bit[29], Channel A Error Status (sticky, read-only) */
int DXS_B :2; /* bit[28:27], Data Buffer Channel B Status */
int DERR_B :1; /* bit[26], Channel B Error Status (sticky) */
int SPTRAN :1; /* bit[25], SPORT Data Direction */
int SPEN_B :1; /* bit[24], SPORT Data Direction */
int BHD :1; /* bit[23], Buffer Hang Disable */
int RSRVD0 :1; /* bit[22], reserved */
int SCHEN_B :1; /* bit[21], DMA Channel B */
int SDEN_B :1; /* bit[20], DMA Channel B Enable */
int SCHEN_A :1; /* bit[19], DMA Channel A */
int SDEN_A :1; /* bit[18], DMA Channel A Enable */
int LAFS :1; /* bit[17], Late Frame Sync */
int FRFS :1; /* bit[16], Active Low Frame Sync */
int DIFS :1; /* bit[15], Data Independent TX FS (if SPTRAN=1) or RX FS (if SPTRAN=0) */
int RSRVD1 :3; /* bit[14:12], reserved */
int OP_MODE :1; /* bit[11], SPORT Operation Mode */
int MSTR :1; /* bit[10], I2S Serial and L/R Clock Master2 */
int PACK :1; /* bit[9], 16/32 Packing */
int SLEN :5; /* bit[8:4], Serial Word Length=1 */
int DTYPE :3; /* bit[3:1], reserved */
int SPEN_A :1; /* bit[0], SPORT Enable A */
} BIT;
} I2S_MODE;

union
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int DXS_A :2; /* bit[31:30], Data Buffer Channel A Status (read-only) */
int DERR_A :1; /* bit[29], Channel A Error Status (sticky, read-only) */
int DXS_B :2; /* bit[28:27], Data Buffer Channel B Status */
int DERR_B :1; /* bit[26], Channel B Error Status (sticky) */
int SPTRAN :1; /* bit[25], SPORT Data Direction */
int RSRVD0 :1; /* bit[24], reserved */
int BHD :1; /* bit[23], Buffer Hang Disable */
int RSRVD1 :1; /* bit[22], reserved */
int SCHEN_B :1; /* bit[21], DMA Channel B */
int SDEN_B :1; /* bit[20], DMA Channel B Enable */
int SCHEN_A :1; /* bit[19], DMA Channel A */
int SDEN_A :1; /* bit[18], DMA Channel A Enable */
int RSRVD2 :1; /* bit[17], reserved */
int LMFS :1; /* bit[16], Active Low Multichannel Frame */
int RSRVD3 :1; /* bit[15], reserved */
int IMFS :1; /* bit[14], Internally Generated Multichannel Frame Sync */
int RSRVD4 :1; /* bit[13], reserved */
int CKRE :1; /* bit[12], Active Clock Edge for Data and Frame Sync Sampling */
int OP_MODE :1; /* bit[11], SPORT Operation Mode */
int ICLK :1; /* bit[10], Internally Generated Clock */
int PACK :1; /* bit[9], 16/32 Packing */
int SLEN :5; /* bit[8:4], Serial Word Length=1 */
int LSBF :1; /* bit[3], Serial Word Bit Order */
int DTYPE :2; /* bit[2:1], Data Type */
int RSRVD5 :1; /* bit[0], reserved */
} BIT;
} I2S_MCH_MODE;
}ST_SPCTL;

typedef union st_div /* SPORT Divisor Registers (DIVx) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int FSDIV :16; /* bit[31:16], Frame Sync Divisor */
int CLKDIV :15; /* bit[15:1], Clock Divisor */
int RSRVD0 :1; /* bit[0], reserved */
} BIT;
}ST_DIV;

typedef union st_spmctl /* SPORT Multichannel Control Registers (SPMCTLx) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int DMACHSxy :4; /* bit[31:28], DMA Chaining Status */
int DMASxy :4; /* bit[27:24], DMA Status */
int MCEB :1; /* bit[23], Multichannel Enable, B Channels */
int CHNL :7; /* bit[22:16], Current Channel Selected (read-only, sticky) */
int RSRVD0 :3; /* bit[15:13], reserved */
int SPL :1; /* bit[12], SPORT Loopback Mode */
int NCH :7; /* bit[11:5], Number of Multichannel Slots (minus one) */
int MFD :4; /* bit[4:1], Multichannel Frame Delay */
int MCEA :1; /* bit[0], Multichannel Mode Enable */
} BIT;
}ST_SPMCTL;

typedef union st_sperrctl /* SPORT Error Control Register (SPERRCTLx) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :26; /* bit[31:6], reserved */
int DERRA_STAT :1; /* bit[5], Channel A Interrupt Status (W1C) */
int DERRB_STAT :1; /* bit[4], Channel B Interrupt Status (W1C) */
int FSERRA_STAT :1; /* bit[3], Frame Sync Interrupt Status (W1C) */
int FSERRA_EN :1; /* bit[2], Enable Frame Sync Error */
int DERRB_EN :1; /* bit[1], Enable Channel B Error */
int DERRA_EN :1; /* bit[0], Enable Channel A Error */
} BIT;
}ST_SPERRCTL;

// SPI Registers
typedef union st_spictl /* SPI Control Registers (SPICTL, SPICTLB) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :11; /* bit[31:21], reserved */
int ILPBK :1; /* bit[20], Internal Loop Back */
int RXFLSH :1; /* bit[19], Clear RXSPI */
int TXFLSH :1; /* bit[18], Flush Transmit Buffer */
int SMLS :1; /* bit[17], Seamless Transfer */
int SGN :1; /* bit[16], Sign Extend */
int PACKEN :1; /* bit[15], PACKEN */
int SPIEN :1; /* bit[14], SPI Port Enable */
int OPD :1; /* bit[13], Open Drain Output Enable */
int SPIMS :1; /* bit[12], SPI Master Select */
int CLKPL :1; /* bit[11], Clock Polarity */
int CPHASE :1; /* bit[10], Clock Phase */
int MSBF :1; /* bit[9], Most Significant Byte First */
int WL :2; /* bit[8:7], Word Length */
int RSRVD1 :1; /* bit[6], reserved */
int DMISO :1; /* bit[5], Disable MISO Pin */
int ISSEN :1; /* bit[4], Input Slave-Select Enable */
int GM :1; /* bit[3], When RXSPI is full, get data or discard incoming data */
int SENDZ :1; /* bit[2], Send zero or the last word when TXSPI is empty */
int TIMOD :2; /* bit[1:0], Transfer Initiation Mode */
} BIT;
}ST_SPICTL;

typedef union st_spibaud /* SPIBAUD, SPIBAUDB Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD1 :16; /* bit[31:16], reserved */
int BAUD_DIVISOR :15; /* bit[15:1], baud rate divisor */
int RSRVD0 :1; /* bit[0], reserved */
} BIT;
}ST_SPIBAUD;

typedef union st_spiflg /* SPI Port Flags Registers (SPIFLG, SPIFLGB) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :20; /* bit[31:12], reserved */
int SPIFLG3 :1; /* bit[11], SPI Device Select Control */
int SPIFLG2 :1; /* bit[10], SPI Device Select Control */
int SPIFLG1 :1; /* bit[9], SPI Device Select Control */
int SPIFLG0 :1; /* bit[8], SPI Device Select Control */
int ISSS :1; /* bit[7], Input Service Select */
int RSRVD1 :3; /* bit[6:4], reserved */
int DS3EN :1; /* bit[3], SPI Device Select Enable */
int DS2EN :1; /* bit[2], SPI Device Select Enable */
int DS1EN :1; /* bit[1], SPI Device Select Enable */
int DS0EN :1; /* bit[0], SPI Device Select Enable */
} BIT;
}ST_SPIFLG;

typedef union st_spistat /* SPI Port Status (SPISTAT, SPISTATB) Registers */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int SPIFE :1; /* bit[7], External Transaction Complete */
int TXCOL :1; /* bit[6], Transmit Collision Error */
int RXS :1; /* bit[5], Receive Data Buffer Status */
int ROVF :1; /* bit[4], Reception Error */
int TXS :1; /* bit[3], Transmit Data Buffer Status */
int TUNF :1; /* bit[2], Transmission Error */
int MME :1; /* bit[1], Multimaster Error or Mode-Fault Error */
int SPIF :1; /* bit[0], SPI Transmit or Receive Transfer Complete */
} BIT;
}ST_SPISTAT;

typedef union st_spidmac /* SPI DMA Configuration Registers (SPIDMAC, SPIDMACB) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :15; /* bit[31:17], reserved */
int SPICHS :1; /* bit[16], DMA Chain Loading Status */
int SPIDMAS :1; /* bit[15], DMA Transfer Status */
int SPIERRS :1; /* bit[14], DMA Error Status */
int SPISx :2; /* bit[13:12], DMA FIFO Status */
int SPIMME :1; /* bit[11], Multimaster Error */
int SPIUNF :1; /* bit[10], Transmit Underflow Error (SPIRCV = 0) */
int SPIOVF :1; /* bit[9], Receive OverFlow Error (SPIRCV = 1) */
int INTERR :1; /* bit[8], Enable Interrupt on Error */
int FIFOFLSH :1; /* bit[7], DMA FIFO Clear */
int RSRVD1 :2; /* bit[6:5], reserved */
int SPICHEN :1; /* bit[4], SPI DMA Chaining Enable */
int RSRVD2 :1; /* bit[3], reserved */
int INTEN :1; /* bit[2], Enable DMA Interrupt on Transfer */
int SPIRCV :1; /* bit[1], DMA Write/Read */
int SPIDEN :1; /* bit[0], DMA Enable */
} BIT;
}ST_SPIDMAC;

// Timer Registers
typedef union st_tmstat /* Timer Global Status and Control (TMSTAT) Register */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :18; /* bit[31:14], reserved */
int TIM2DIS :1; /* bit[13], Timer 2 Disable */
int TIM2EN :1; /* bit[12], Timer 2 Enable */
int TIM1DIS :1; /* bit[11], Timer 1 Disable */
int TIM1EN :1; /* bit[10], Timer 1 Enable */
int TIM0DIS :1; /* bit[9], Timer 0 Disable */
int TIM0EN :1; /* bit[8], Timer 0 Enable */
int RSRVD1 :1; /* bit[7], reserved */
int TIM2OVF :1; /* bit[6], Timer 2 Overflow/Error */
int TIM1OVF :1; /* bit[5], Timer 1 Overflow/Error */
int TIM0OVF :1; /* bit[4], Timer 0 Overflow/Error */
int RSRVD2 :1; /* bit[3], reserved */
int TIM2IRQ :1; /* bit[2], Timer 2 Interrupt Latch */
int TIM1IRQ :1; /* bit[1], Timer 1 Interrupt Latch */
int TIM0IRQ :1; /* bit[0], Timer 0 Interrupt Latch */
} BIT;
}ST_TMSTAT;

typedef union st_tmctl /* Timer Configuration Registers (TMxCTL) */
{
int ALL; /* all 32 bits */
struct
{
int RSRVD0 :26; /* bit[31:6], reserved */
int AUX :1; /* bit[5], Timer Input Select */
int IRQEN :1; /* bit[4], Interrupt Enable */
int PRDCNT :1; /* bit[3], Period Count */
int PULSE :1; /* bit[2], Pulse Edge Select */
int TIMODE :2; /* bit[1:0], Timer Mode */
} BIT;
}ST_TMCTL;

// POWER MGT Registers
typedef union st_pmctl /* Power Management Control Register (PMCTL) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int TMEROFF :1; /* bit[31], Timer Enable/Disable */
int SPIOFF :1; /* bit[30], SPI Enable/Disable */
int SP45OFF :1; /* bit[29], SPORT4, 5 Enable/Disable */
int SP23OFF :1; /* bit[28], SPORT2, 3 Enable/Disable */
int SP01OFF :1; /* bit[27], SPORT0, 1 Enable/Disable */
int PPPDN :1; /* bit[26], External Port Enable/Disable */
int SRCOFF :1; /* bit[25], SRC Off */
int DTCPOFF :1; /* bit[24], DTCP Clock Enable */
int PWMOFF :1; /* bit[23], PWM Clock Enable */
int SDRAMOFF :1; /* bit[22], SDRAM Clock Enable */
int TWIOFF :1; /* bit[21], TWI Clock Enable */
int SDCKR :3; /* bit[20:18], SDCLK Ratio */
int CRAT1 :1; /* bit[17], PLL Clock Ratio, CLKIN to CK (read only) */
int CRAT0 :1; /* bit[16], PLL Clock Ratio, CLKIN to CK (read only) */
int PLLBP :1; /* bit[15], PLL Bypass Mode Indication */
int UART1OFF :1; /* bit[14], UART1 Clock Enable */
int UART0OFF :1; /* bit[13], UART0 Clock Enable */
int CLKOUTEN :1; /* bit[12], Clockout Enable */
int SP67OFF :1; /* bit[11], Serial Port 6, 7 Clock Enable */
int RSRVD0 :1; /* bit[10], reserved */
int DIVEN :1; /* bit[9], Enable PLL Divider Value Loading (read/write) */
int INDIV :1; /* bit[8], Input Divisor (read/write) */
int PLLD :2; /* bit[7:6], PLL Divider (read/write) */
int PLLM :6; /* bit[5:0], PLL Multiplier (read/write) */
} BIT;
}ST_PMCTL;

// SRU Registers
typedef union st_sru_clk0 /* SRU Clock Control Register 0 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPORT5_CLK_I :5; /* bit[29:25], Serial Port 5 Clock Input */
int SPORT4_CLK_I :5; /* bit[24:20], Serial Port 4 Clock Input */
int SPORT3_CLK_I :5; /* bit[19:15], Serial Port 3 Clock Input */
int SPORT2_CLK_I :5; /* bit[14:10], Serial Port 2 Clock Input */
int SPORT1_CLK_I :5; /* bit[9:5], Serial Port 1 Clock Input */
int SPORT0_CLK_I :5; /* bit[4:0], Serial Port 0 Clock Input */
} BIT;
}ST_SRU_CLK0;

typedef union st_sru_clk1 /* SRU Clock Control Register 1 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SRC2_CLK_OP_I :5; /* bit[29:25], Sample Rate Converter 2 Clock Output Input */
int SRC2_CLK_IP_I :5; /* bit[24:20], Sample Rate Converter 2 Clock Input Input */
int SRC1_CLK_OP_I :5; /* bit[19:15], Sample Rate Converter 1 Clock Output Input */
int SRC1_CLK_IP_I :5; /* bit[14:10], Sample Rate Converter 1 Clock Input Input */
int SRC0_CLK_OP_I :5; /* bit[9:5], Sample Rate Converter 0 Clock Output Input */
int SRC0_CLK_IP_I :5; /* bit[4:0], Sample Rate Converter 0 Clock Input Input */
} BIT;
}ST_SRU_CLK1;

typedef union st_sru_clk2 /* SRU Clock Control Register 2 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int IDP2_CLK_I :5; /* bit[29:25], Input Data Port 2 Clock Input */
int IDP1_CLK_I :5; /* bit[24:20], Input Data Port 1 Clock Input */
int IDP0_CLK_I :5; /* bit[19:15], Input Data Port 0 Clock Input */
int DIT_CLK_I :5; /* bit[14:10], SPDIF Transmitter Clock Input */
int SRC3_CLK_OP_I :5; /* bit[9:5], Sample Rate Converter 3 Clock Output Input */
int SRC3_CLK_IP_I :5; /* bit[4:0], Sample Rate Converter 3 Clock Input Input */
} BIT;
}ST_SRU_CLK2;

typedef union st_sru_clk3 /* SRU Clock Control Register 3 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DIT_HFCLK_I :5; /* bit[29:25], SPDIF Oversampling Clock Input */
int IDP7_CLK_I :5; /* bit[24:20], Input Data Port Channel 7 Clock Input */
int IDP6_CLK_I :5; /* bit[19:15], Input Data Port Channel 6 Clock Input */
int IDP5_CLK_I :5; /* bit[14:10], Input Data Port Channel 5 Clock Input */
int IDP4_CLK_I :5; /* bit[9:5], Input Data Port Channel 4 Clock Input */
int IDP3_CLK_I :5; /* bit[4:0], Input Data Port Channel 3 Clock Input */
} BIT;
}ST_SRU_CLK3;

typedef union st_sru_clk4 /* SRU Clock Control Register 4 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PCG_SYNC_CLKB_I :5; /* bit[29:25], Precision Clock Generator Clock B Sync Input */
int PCG_SYNC_CLKA_I :5; /* bit[24:20], Precision Clock Generator Clock A Sync Input */
int RSRVD1 :5; /* bit[19:15], reserved */
int SPDIF_EXTPLLCLK_I:5; /* bit[14:10], External 512 x FS PLL Clock Input */
int PCG_EXTB_I :5; /* bit[9:5], Precision Clock Generator External Clock B Input */
int PCG_EXTA_I :5; /* bit[4:0], Precision Clock Generator External Clock A Input */
} BIT;
}ST_SRU_CLK4;

typedef union st_sru_clk5 /* SRU Clock Control Register 5 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PCG_EXTD_I :5; /* bit[29:25], Precision Clock Generator External Clock D Input */
int PCG_EXTC_I :5; /* bit[24:20], Precision Clock Generator External Clock C Input */
int PCG_SYNC_CLKD_I :5; /* bit[19:15], Precision Clock Generator Clock D Sync Input */
int PCG_SYNC_CLKC_I :5; /* bit[14:10], Precision Clock Generator Clock C Sync Input */
int SPORT7_CLK_I :5; /* bit[9:5], Serial Port 7 Clock Input */
int SPORT6_CLK_I :5; /* bit[4:0], Serial Port 6 Clock Input */
} BIT;
}ST_SRU_CLK5;

typedef union st_sru_dat0 /* SRU Data Control Register 0 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPORT2_DA_I :6; /* bit[29:24], Serial Port 2 Data Channel A Input */
int SPORT1_DB_I :6; /* bit[23:18], Serial Port 1 Data Channel B Input */
int SPORT1_DA_I :6; /* bit[17:12], Serial Port 1 Data Channel A Input */
int SPORT0_DB_I :6; /* bit[11:6], Serial Port 0 Data Channel B Input */
int SPORT0_DA_I :6; /* bit[5:0], Serial Port 0 Data Channel A Input */
} BIT;
}ST_SRU_DAT0;

typedef union st_sru_dat1 /* SRU Data Control Register 1 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPORT4_DB_I :6; /* bit[29:24], Serial Port 4 Data Channel B Input */
int SPORT4_DA_I :6; /* bit[23:18], Serial Port 4 Data Channel A Input */
int SPORT3_DB_I :6; /* bit[17:12], Serial Port 3 Data Channel B Input */
int SPORT3_DA_I :6; /* bit[11:6], Serial Port 3 Data Channel A Input */
int SPORT2_DB_I :6; /* bit[5:0], Serial Port 2 Data Channel B Input */
} BIT;
}ST_SRU_DAT1;

typedef union st_sru_dat2 /* SRU Data Control Register 2 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SRC2_DAT_IP_I :6; /* bit[29:24], Sample Rate Converter 2 Data Input Input */
int SRC1_DAT_IP_I :6; /* bit[23:18], Sample Rate Converter 1 Data Input Input */
int SRC0_DAT_IP_I :6; /* bit[17:12], Sample Rate Converter 0 Data Input Input */
int SPORT5_DB_I :6; /* bit[11:6], Serial Port 5 Data Channel B Input */
int SPORT5_DA_I :6; /* bit[5:0], Serial Port 5 Data Channel A Input */
} BIT;
}ST_SRU_DAT2;

typedef union st_sru_dat3 /* SRU Data Control Register 3 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SRC3_TDM_OP_I :6; /* bit[29:24], Sample Rate Converter 3 TDM Output Input */
int SRC2_TDM_OP_I :6; /* bit[23:18], Sample Rate Converter 2 TDM Output Input */
int SRC1_TDM_OP_I :6; /* bit[17:12], Sample Rate Converter 1 TDM Output Input */
int SRC0_TDM_OP_I :6; /* bit[11:6], Sample Rate Converter 0 TDM Output Input */
int SRC3_DAT_IP_I :6; /* bit[5:0], Sample Rate Converter 3 Data Input Inpu */
} BIT;
}ST_SRU_DAT3;

typedef union st_sru_dat4 /* SRU Data Control Register 4 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int IDP3_DAT_I :6; /* bit[29:24], Input Data Port 3 Data Input */
int IDP2_DAT_I :6; /* bit[23:18], Input Data Port 2 Data Input */
int IDP1_DAT_I :6; /* bit[17:12], Input Data Port 1 Data Input */
int IDP0_DAT_I :6; /* bit[11:6], Input Data Port 0 Data Input */
int DIT_DAT_I :6; /* bit[5:0], SPDIF Transmit Data Input */
} BIT;
}ST_SRU_DAT4;

typedef union st_sru_dat5 /* SRU Data Control Register 5 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DIR_DAT_I :6; /* bit[29:24], SPDIF Receive Data Input */
int IDP7_DAT_I :6; /* bit[23:18], Input Data Port 7 Data Input */
int IDP6_DAT_I :6; /* bit[17:12], Input Data Port 6 Data Input */
int IDP5_DAT_I :6; /* bit[11:6], Input Data Port 5 Data Input */
int IDP4_DAT_I :6; /* bit[5:0], Input Data Port 4 Data Channel A Input */
} BIT;
}ST_SRU_DAT5;

typedef union st_sru_dat6 /* SRU Data Control Register 6 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :8; /* bit[31:24], reserved */
int SPORT7_DB_I :6; /* bit[23:18], Serial Port 7 Data Channel B Input */
int SPORT7_DA_I :6; /* bit[17:12], Serial Port 7 Data Channel A Input */
int SPORT6_DB_I :6; /* bit[11:6], Serial Port 6 Data Channel B Input */
int SPORT6_DA_I :6; /* bit[5:0], Serial Port 6 Data Channel A Input Input */
} BIT;
}ST_SRU_DAT6;

typedef union st_sru_fs0 /* SRU FS Control Register 0 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPORT5_FS_I :5; /* bit[29:25], Serial Port 5 Frame Sync Input */
int SPORT4_FS_I :5; /* bit[24:20], Serial Port 4 Frame Sync Input */
int SPORT3_FS_I :5; /* bit[19:15], Serial Port 3 Frame Sync Input */
int SPORT2_FS_I :5; /* bit[14:10], Serial Port 2 Frame Sync Input */
int SPORT1_FS_I :5; /* bit[9:5], Serial Port 1 Frame Sync Input */
int SPORT0_FS_I :5; /* bit[4:0], Serial Port 0 Frame Sync Input */
} BIT;
}ST_SRU_FS0;

typedef union st_sru_fs1 /* SRU FS Control Register 1 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SRC2_FS_OP_I :5; /* bit[29:25], Sample Rate Converter 2 Frame Sync Output Input */
int SRC2_FS_IP_I :5; /* bit[24:20], Sample Rate Converter 2 Frame Sync Input Input */
int SRC1_FS_OP_I :5; /* bit[19:15], Sample Rate Converter 1 Frame Sync Output Input */
int SRC1_FS_IP_I :5; /* bit[14:10], Sample Rate Converter 1 Frame Sync Input Input */
int SRC0_FS_OP_I :5; /* bit[9:5], Sample Rate Converter 0 Frame Sync Output Input */
int SRC0_FS_IP_I :5; /* bit[4:0], Sample Rate Converter 0 Frame Sync Input Input */
} BIT;
}ST_SRU_FS1;

typedef union st_sru_fs2 /* SRU FS Control Register 2 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int IDP2_FS_I :5; /* bit[29:25], Input Data Port Channel 2 Frame Sync Input */
int IDP1_FS_I :5; /* bit[24:20], Input Data Port Channel 1 Frame Sync Input */
int IDP0_FS_I :5; /* bit[19:15], Input Data Port Channel 0 Frame Sync Input */
int SPDIF_TX_FS_I :5; /* bit[14:10], SPDIF 3 Oversampling Clock Input */
int SRC3_FS_OP_I :5; /* bit[9:5], Sample Rate Converter 3 Frame Sync Output Input */
int SRC3_FS_IP_I :5; /* bit[4:0], Sample Rate Converter 3 Frame Sync Input Input */
} BIT;
}ST_SRU_FS2;

typedef union st_sru_fs3 /* SRU FS Control Register 3 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPDIF_RX_I :5; /* bit[29:25], SPDIF Receiver Biphase Encoded Data Input */
int IDP7_FS_I :5; /* bit[24:20], Input Data Port Channel 7 Frame Sync Input */
int IDP6_FS_I :5; /* bit[19:15], Input Data Port Channel 6 Frame Sync Input */
int IDP5_FS_I :5; /* bit[14:10], Input Data Port Channel 5 Frame Sync Input */
int IDP4_FS_I :5; /* bit[9:5], Input Data Port Channel 4 Frame Sync Input */
int IDP3_FS_I :5; /* bit[4:0], Input Data Port Channel 3 Frame Sync Input */
} BIT;
}ST_SRU_FS3;

typedef union st_sru_fs4 /* SRU FS Control Register 4 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :22; /* bit[31:10], reserved */
int SPORT7_FS_I :5; /* bit[9:5], Serial Port 7 Frame Sync Input */
int SPORT6_FS_I :5; /* bit[4:0], Serial Port 6 Frame Sync Input */
} BIT;
}ST_SRU_FS4;

typedef union st_sru_pin0 /* SRU Pin Control Register 0 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int DAI_PB04_I :7; /* bit[27:21], DAI Pin Buffer 4 Input */
int DAI_PB03_I :7; /* bit[20:14], DAI Pin Buffer 3 Input */
int DAI_PB02_I :7; /* bit[13:7], DAI Pin Buffer 2 Input */
int DAI_PB01_I :7; /* bit[6:0], DAI Pin Buffer 1 Input */
} BIT;
}ST_SRU_PIN0;

typedef union st_sru_pin1 /* SRU Pin Control Register 1 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int DAI_PB08_I :7; /* bit[27:21], DAI Pin Buffer 8 Input */
int DAI_PB07_I :7; /* bit[20:14], DAI Pin Buffer 7 Input */
int DAI_PB06_I :7; /* bit[13:7], DAI Pin Buffer 6 Input */
int DAI_PB05_I :7; /* bit[6:0], DAI Pin Buffer 5 Input */
} BIT;
}ST_SRU_PIN1;

typedef union st_sru_pin2 /* SRU Pin Control Register 2 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int DAI_PB12_I :7; /* bit[27:21], DAI Pin Buffer 12 Input */
int DAI_PB11_I :7; /* bit[20:14], DAI Pin Buffer 11 Input */
int DAI_PB10_I :7; /* bit[13:7], DAI Pin Buffer 10 Input */
int DAI_PB09_I :7; /* bit[6:0], DAI Pin Buffer 9 Input */
} BIT;
}ST_SRU_PIN2;

typedef union st_sru_pin3 /* SRU Pin Control Register 3 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int DAI_PB16_I :7; /* bit[27:21], DAI Pin Buffer 16 Input */
int DAI_PB15_I :7; /* bit[20:14], DAI Pin Buffer 15 Input */
int DAI_PB14_I :7; /* bit[13:7], DAI Pin Buffer 14 Input */
int DAI_PB13_I :7; /* bit[6:0], DAI Pin Buffer 13 Input */
} BIT;
}ST_SRU_PIN3;

typedef union st_sru_pin4 /* SRU Pin Control Register 4 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :4; /* bit[31:28], reserved */
int DAI_PB20_I :7; /* bit[27:21], DAI Pin Buffer 20 Input */
int DAI_PB19_I :7; /* bit[20:14], DAI Pin Buffer 19 Input */
int DAI_PB18_I :7; /* bit[13:7], DAI Pin Buffer 18 Input */
int DAI_PB17_I :7; /* bit[6:0], DAI Pin Buffer 17 Input */
} BIT;
}ST_SRU_PIN4;

typedef union st_sru_ext_misca /* SRU External Misc. A Control Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int MISCA5_INVERT :1; /* bit[31], Invert Miscellaneous Channel A 5 */
int MISCA4_INVERT :1; /* bit[30], Invert Miscellaneous Channel A 4 */
int MISCA5_I :5; /* bit[29:25], External Miscellaneous Channel A 5 */
int MISCA4_I :5; /* bit[24:20], External Miscellaneous Channel A 4 */
int MISCA3_I :5; /* bit[19:15], External Miscellaneous Channel A 3, DAI Interrupt 31 */
int MISCA2_I :5; /* bit[14:10], External Miscellaneous Channel A 2, DAI Interrupt 30 */
int MISCA1_I :5; /* bit[9:5], External Miscellaneous Channel A 1, DAI Interrupt 29 */
int MISCA0_I :5; /* bit[4:0], External Miscellaneous Channel A 0, DAI Interrupt 28 */
} BIT;
}ST_SRU_MISCA;

typedef union st_sru_ext_miscb /* SRU External Misc. B Control Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DAI_INT_27 :5; /* bit[29:25], DAI Interrupt 27 */
int DAI_INT_26 :5; /* bit[24:20], DAI Interrupt 26 */
int DAI_INT_25 :5; /* bit[19:15], DAI Interrupt 25 */
int DAI_INT_24 :5; /* bit[14:10], DAI Interrupt 24 */
int DAI_INT_23 :5; /* bit[9:5], DAI Interrupt 23 */
int DAI_INT_22 :5; /* bit[4:0], DAI Interrupt 22 */
} BIT;
}ST_SRU_MISCB;

typedef union st_sru_pben0 /* SRU Pin Enable Register 0 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PBEN05I :6; /* bit[29:24], DAI Port 5 Pin Buffer Enable Input */
int PBEN04I :6; /* bit[23:18], DAI Port 4 Pin Buffer Enable Input */
int PBEN03I :6; /* bit[17:12], DAI Port 3 Pin Buffer Enable Input */
int PBEN02I :6; /* bit[11:6], DAI Port 2 Pin Buffer Enable Input */
int PBEN01I :6; /* bit[5:0], DAI Port 1 Pin Buffer Enable Input */
} BIT;
}ST_SRU_PBEN0;

typedef union st_sru_pben1 /* SRU Pin Enable Register 1 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PBEN10I :6; /* bit[29:24], DAI Port 10 Pin Buffer Enable Input */
int PBEN09I :6; /* bit[23:18], DAI Port 9 Pin Buffer Enable Input */
int PBEN08I :6; /* bit[17:12], DAI Port 8 Pin Buffer Enable Input */
int PBEN07I :6; /* bit[11:6], DAI Port 7 Pin Buffer Enable Input */
int PBEN06I :6; /* bit[5:0], DAI Port 6 Pin Buffer Enable Input */
} BIT;
}ST_SRU_PBEN1;

typedef union st_sru_pben2 /* SRU Pin Enable Register 2 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PBEN15I :6; /* bit[29:24], DAI Port 15 Pin Buffer Enable Input */
int PBEN14I :6; /* bit[23:18], DAI Port 14 Pin Buffer Enable Input */
int PBEN13I :6; /* bit[17:12], DAI Port 13 Pin Buffer Enable Input */
int PBEN12I :6; /* bit[11:6], DAI Port 12 Pin Buffer Enable Input */
int PBEN11I :6; /* bit[5:0], DAI Port 11 Pin Buffer Enable Input */
} BIT;
}ST_SRU_PBEN2;

typedef union st_sru_pben3 /* SRU Pin Enable Register 3 */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int PBEN20I :6; /* bit[29:24], DAI Port 20 Pin Buffer Enable Input */
int PBEN19I :6; /* bit[23:18], DAI Port 19 Pin Buffer Enable Input */
int PBEN18I :6; /* bit[17:12], DAI Port 18 Pin Buffer Enable Input */
int PBEN17I :6; /* bit[11:6], DAI Port 17 Pin Buffer Enable Input */
int PBEN16I :6; /* bit[5:0], DAI Port 16 Pin Buffer Enable Input */
} BIT;
}ST_SRU_PBEN3;

typedef union st_dai_pin_pullup /* DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :12; /* bit[31:20], reserved */
int DAI_P20_PULLUP :1; /* bit[19], Setting to 1 enables a pull-up resistor */
int DAI_P19_PULLUP :1; /* bit[18], Setting to 1 enables a pull-up resistor */
int DAI_P18_PULLUP :1; /* bit[17], Setting to 1 enables a pull-up resistor */
int DAI_P17_PULLUP :1; /* bit[16], Setting to 1 enables a pull-up resistor */
int DAI_P16_PULLUP :1; /* bit[15], Setting to 1 enables a pull-up resistor */
int DAI_P15_PULLUP :1; /* bit[14], Setting to 1 enables a pull-up resistor */
int DAI_P14_PULLUP :1; /* bit[13], Setting to 1 enables a pull-up resistor */
int DAI_P13_PULLUP :1; /* bit[12], Setting to 1 enables a pull-up resistor */
int DAI_P12_PULLUP :1; /* bit[11], Setting to 1 enables a pull-up resistor */
int DAI_P11_PULLUP :1; /* bit[10], Setting to 1 enables a pull-up resistor */
int DAI_P10_PULLUP :1; /* bit[9], Setting to 1 enables a pull-up resistor */
int DAI_P09_PULLUP :1; /* bit[8], Setting to 1 enables a pull-up resistor */
int DAI_P08_PULLUP :1; /* bit[7], Setting to 1 enables a pull-up resistor */
int DAI_P07_PULLUP :1; /* bit[6], Setting to 1 enables a pull-up resistor */
int DAI_P06_PULLUP :1; /* bit[5], Setting to 1 enables a pull-up resistor */
int DAI_P05_PULLUP :1; /* bit[4], Setting to 1 enables a pull-up resistor */
int DAI_P04_PULLUP :1; /* bit[3], Setting to 1 enables a pull-up resistor */
int DAI_P03_PULLUP :1; /* bit[2], Setting to 1 enables a pull-up resistor */
int DAI_P02_PULLUP :1; /* bit[1], Setting to 1 enables a pull-up resistor */
int DAI_P01_PULLUP :1; /* bit[0], Setting to 1 enables a pull-up resistor */
} BIT;
}ST_SRU_PULLUP;

typedef union st_dai_irptl /* DAI Interrupt Controller Registers */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int SRU_EXTMISCA3_INT:1; /* bit[31], */
int SRU_EXTMISCA2_INT:1; /* bit[30], */
int SRU_EXTMISCA1_INT:1; /* bit[29], */
int SRU_EXTMISCA0_INT:1; /* bit[28], */
int SRU_EXTMISCB5_INT:1; /* bit[27], */
int SRU_EXTMISCB4_INT:1; /* bit[26], */
int SRU_EXTMISCB3_INT:1; /* bit[25], */
int SRU_EXTMISCB2_INT:1; /* bit[24], */
int SRU_EXTMISCB1_INT:1; /* bit[23], */
int SRU_EXTMISCB0_INT:1; /* bit[22], */
int SRC3_MUTE_INT :1; /* bit[21], */
int SRC2_MUTE_INT :1; /* bit[20], */
int SRC1_MUTE_INT :1; /* bit[19], */
int SRC0_MUTE_INT :1; /* bit[18], */
int IDP_DMA7_INT :1; /* bit[17], */
int IDP_DMA6_INT :1; /* bit[16], */
int IDP_DMA5_INT :1; /* bit[15], */
int IDP_DMA4_INT :1; /* bit[14], */
int IDP_DMA3_INT :1; /* bit[13], */
int IDP_DMA2_INT :1; /* bit[12], */
int IDP_DMA1_INT :1; /* bit[11], */
int IDP_DMA0_INT :1; /* bit[10], */
int IDP_FIFO_OVR_INT:1; /* bit[9], */
int IDP_FIFO_GTN_INT:1; /* bit[8], */
int SPDIF_RX_CH_STAT_CHNG:1; /* bit[7], */
int SPDIF_RX_PARITY_ERROR:1; /* bit[6], */
int SPDIF_RX_EMPHASIS:1; /* bit[5], */
int SPDIF_RX_NON_AUDIO:1; /* bit[4], */
int SPDIF_RX_CRC_ERROR:1; /* bit[3], */
int SPDIF_RX_NO_STREAM:1; /* bit[2], */
int SPDIF_RX_LOCK_START:1; /* bit[1], */
int SPDIF_RX_VALID :1; /* bit[0], */
} BIT;
}ST_DAI_IRPTL;

//Input Data Port Register
typedef union st_idp_ctl0 /* Input Data Port Control Register 0 (IDP_CTL0) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int IDP_SMODE7 :3; /* bit[31:29], Serial Input Mode Select */
int IDP_SMODE6 :3; /* bit[28:26], Serial Input Mode Select */
int IDP_SMODE5 :3; /* bit[25:23], Serial Input Mode Select */
int IDP_SMODE4 :3; /* bit[22:20], Serial Input Mode Select */
int IDP_SMODE3 :3; /* bit[19:17], Serial Input Mode Select */
int IDP_SMODE2 :3; /* bit[16:14], Serial Input Mode Select */
int IDP_SMODE1 :3; /* bit[13:11], Serial Input Mode Select */
int IDP_SMODE0 :3; /* bit[10:8], Serial Input Mode Select */
int IDP_ENABLE :1; /* bit[7], Enable IDP. 1 to 0 transition on this bit clears IDP_FIFO. */
int IDP_CLROVR :1; /* bit[6], FIFO Overflow Clear Bit */
int IDP_DMA_EN :1; /* bit[5], DMA Enable. Enables DMA on all IDP channels */
int IDP_BHD :1; /* bit[4], IDP Buffer Hang Disable */
int IDP_NSET :4; /* bit[3:0], Monitors number of FIFO entries where N > samples */
/* raises interrupt controller bit 8 */
} BIT;
}ST_IDP_CTL0;

typedef union st_idp_ctl1 /* Input Data Port Control Register 1 (IDP_CTL1) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int IDP_FFCLR :1; /* bit[31], Clear IDP FIFO */
int RSRVD0 :7; /* bit[30:24], reserved */
int IDP_PING7 :1; /* bit[23], DMA Channel 7 Ping-Pong Enable */
int IDP_PING6 :1; /* bit[22], DMA Channel 6 Ping-Pong Enable */
int IDP_PING5 :1; /* bit[21], DMA Channel 5 Ping-Pong Enable */
int IDP_PING4 :1; /* bit[20], DMA Channel 4 Ping-Pong Enable */
int IDP_PING3 :1; /* bit[19], DMA Channel 3 Ping-Pong Enable */
int IDP_PING2 :1; /* bit[18], DMA Channel 2 Ping-Pong Enable */
int IDP_PING1 :1; /* bit[17], DMA Channel 1 Ping-Pong Enable */
int IDP_PING0 :1; /* bit[16], DMA Channel 0 Ping-Pong Enable */
int IDP_DMA_EN7 :1; /* bit[15], IDP DMA Channel 7 Enable */
int IDP_DMA_EN6 :1; /* bit[14], IDP DMA Channel 6 Enable */
int IDP_DMA_EN5 :1; /* bit[13], IDP DMA Channel 5 Enable */
int IDP_DMA_EN4 :1; /* bit[12], IDP DMA Channel 4 Enable */
int IDP_DMA_EN3 :1; /* bit[11], IDP DMA Channel 3 Enable */
int IDP_DMA_EN2 :1; /* bit[10], IDP DMA Channel 2 Enable */
int IDP_DMA_EN1 :1; /* bit[9], IDP DMA Channel 1 Enable */
int IDP_DMA_EN0 :1; /* bit[8], IDP DMA Channel 0 Enable */
int IDP_EN7 :1; /* bit[7], IDP Channel 7 Enable */
int IDP_EN6 :1; /* bit[6], IDP Channel 6 Enable */
int IDP_EN5 :1; /* bit[5], IDP Channel 5 Enable */
int IDP_EN4 :1; /* bit[4], IDP Channel 4 Enable */
int IDP_EN3 :1; /* bit[3], IDP Channel 3 Enable */
int IDP_EN2 :1; /* bit[2], IDP Channel 2 Enable */
int IDP_EN1 :1; /* bit[1], IDP Channel 1 Enable */
int IDP_EN0 :1; /* bit[0], IDP Channel 0 Enable */
} BIT;
}ST_IDP_CTL1;

typedef union st_idp_pp_ctl /* Parallel Data Acquisition Port Control Register (IDP_PP_CTL) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int IDP_PDAP_EN :1; /* bit[31], PDAP Enable */
int IDP_PDAP_RESET :1; /* bit[30], PDAP Reset */
int IDP_PDAP_CLKEDGE:1; /* bit[29], PDAP (Rising or Falling) Clock Edge */
int IDP_PDAP_PACKING:2; /* bit[28:27], Selects PDAP packing mode */
int IDP_PORT_SELECT :1; /* bit[26], Port Select: Input Pins Select */
int RSRVD0 :6; /* bit[25:20], reserved */
int IDP_P20_PDAPMASK:1; /* bit[19], Parallel Data Acquisition Port Mask */
int IDP_P19_PDAPMASK:1; /* bit[18], Parallel Data Acquisition Port Mask */
int IDP_P18_PDAPMASK:1; /* bit[17], Parallel Data Acquisition Port Mask */
int IDP_P17_PDAPMASK:1; /* bit[16], Parallel Data Acquisition Port Mask */
int IDP_P16_PDAPMASK:1; /* bit[15], Parallel Data Acquisition Port Mask */
int IDP_P15_PDAPMASK:1; /* bit[14], Parallel Data Acquisition Port Mask */
int IDP_P14_PDAPMASK:1; /* bit[13], Parallel Data Acquisition Port Mask */
int IDP_P13_PDAPMASK:1; /* bit[12], Parallel Data Acquisition Port Mask */
int IDP_P12_PDAPMASK:1; /* bit[11], Parallel Data Acquisition Port Mask */
int IDP_P11_PDAPMASK:1; /* bit[10], Parallel Data Acquisition Port Mask */
int IDP_P10_PDAPMASK:1; /* bit[9], Parallel Data Acquisition Port Mask */
int IDP_P09_PDAPMASK:1; /* bit[8], Parallel Data Acquisition Port Mask */
int IDP_P08_PDAPMASK:1; /* bit[7], Parallel Data Acquisition Port Mask */
int IDP_P07_PDAPMASK:1; /* bit[6], Parallel Data Acquisition Port Mask */
int IDP_P06_PDAPMASK:1; /* bit[5], Parallel Data Acquisition Port Mask */
int IDP_P05_PDAPMASK:1; /* bit[4], Parallel Data Acquisition Port Mask */
int IDP_P04_PDAPMASK:1; /* bit[3], Parallel Data Acquisition Port Mask */
int IDP_P03_PDAPMASK:1; /* bit[2], Parallel Data Acquisition Port Mask */
int IDP_P02_PDAPMASK:1; /* bit[1], Parallel Data Acquisition Port Mask */
int IDP_P01_PDAPMASK:1; /* bit[0], Parallel Data Acquisition Port Mask */
} BIT;
}ST_IDP_PP_CTL;

typedef union st_dai_stat /* DAI Status Register */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int IDP_FIFOSZ :4; /* bit[31:28], Number of samples in the IDP FIFO */
int RSRVD0 :3; /* bit[27:25], reserved */
int IDP_DMA7_STAT :1; /* bit[24], Input Data Port DMA 7 Status */
int IDP_DMA6_STAT :1; /* bit[23], Input Data Port DMA 6 Status */
int IDP_DMA5_STAT :1; /* bit[22], Input Data Port DMA 5 Status */
int IDP_DMA4_STAT :1; /* bit[21], Input Data Port DMA 4 Status */
int IDP_DMA3_STAT :1; /* bit[20], Input Data Port DMA 3 Status */
int IDP_DMA2_STAT :1; /* bit[19], Input Data Port DMA 2 Status */
int IDP_DMA1_STAT :1; /* bit[18], Input Data Port DMA 1 Status */
int IDP_DMA0_STAT :1; /* bit[17], Input Data Port DMA 0 Status */
int RSRVD1 :1; /* bit[16], reserved */
int SRU_OVF7 :1; /* bit[15], Sticky Overflow Status (Channel 7) */
int SRU_OVF6 :1; /* bit[14], Sticky Overflow Status (Channel 6) */
int SRU_OVF5 :1; /* bit[13], Sticky Overflow Status (Channel 5) */
int SRU_OVF4 :1; /* bit[12], Sticky Overflow Status (Channel 4) */
int SRU_OVF3 :1; /* bit[11], Sticky Overflow Status (Channel 3) */
int SRU_OVF2 :1; /* bit[10], Sticky Overflow Status (Channel 2) */
int SRU_OVF1 :1; /* bit[9], Sticky Overflow Status (Channel 1) */
int SRU_OVF0 :1; /* bit[8], Sticky Overflow Status (Channel 0) */
int SRU_PING7_STAT :1; /* bit[7], Ping-pong DMA Status (Channel 7) */
int SRU_PING6_STAT :1; /* bit[6], Ping-pong DMA Status (Channel 6) */
int SRU_PING5_STAT :1; /* bit[5], Ping-pong DMA Status (Channel 5) */
int SRU_PING4_STAT :1; /* bit[4], Ping-pong DMA Status (Channel 4) */
int SRU_PING3_STAT :1; /* bit[3], Ping-pong DMA Status (Channel 3) */
int SRU_PING2_STAT :1; /* bit[2], Ping-pong DMA Status (Channel 2) */
int SRU_PING1_STAT :1; /* bit[1], Ping-pong DMA Status (Channel 1) */
int SRU_PING0_STAT :1; /* bit[0], Ping-pong DMA Status (Channel 0) */
} BIT;
}ST_DAI_STAT;

typedef union st_dai_pin_stat /* DAI Pin Buffer Status Register (DAI_PIN_STAT) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :12; /* bit[31:20], reserved */
int DAI_PB20 :1; /* bit[19], DAI PB20 Status */
int DAI_PB19 :1; /* bit[18], DAI PB19 Status */
int DAI_PB18 :1; /* bit[17], DAI PB18 Status */
int DAI_PB17 :1; /* bit[16], DAI PB17 Status */
int DAI_PB16 :1; /* bit[15], DAI PB16 Status */
int DAI_PB15 :1; /* bit[14], DAI PB15 Status */
int DAI_PB14 :1; /* bit[13], DAI PB14 Status */
int DAI_PB13 :1; /* bit[12], DAI PB13 Status */
int DAI_PB12 :1; /* bit[11], DAI PB12 Status */
int DAI_PB11 :1; /* bit[10], DAI PB11 Status */
int DAI_PB10 :1; /* bit[9], DAI PB10 Status */
int DAI_PB09 :1; /* bit[8], DAI PB9 Status */
int DAI_PB08 :1; /* bit[7], DAI PB8 Status */
int DAI_PB07 :1; /* bit[6], DAI PB7 Status */
int DAI_PB06 :1; /* bit[5], DAI PB6 Status */
int DAI_PB05 :1; /* bit[4], DAI PB5 Status */
int DAI_PB04 :1; /* bit[3], DAI PB4 Status */
int DAI_PB03 :1; /* bit[2], DAI PB3 Status */
int DAI_PB02 :1; /* bit[1], DAI PB2 Status */
int DAI_PB01 :1; /* bit[0], DAI PB1 Status */
} BIT;
}ST_DAI_PIN_STAT;

typedef union st_idp_fifo /* Input Data Port FIFO Register (IDP_FIFO) */
{
int ALL; /* all 32 bits */
struct
{
int H :16;
int L :16;
} WORD;
struct
{
int DATA :28; /* bit[31:4], Input Data (Serial) */
int LR_STAT :1; /* bit[3], Left/Right channel as specified by frame sync */
int CH :3; /* bit[2:0], IDP Channel Encoding */
} BIT;
}ST_IDP_FIFO;

//DPI Registers
typedef union st_sru2_input0 /* SRU2_INPUT0 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int SPIB_MISO_I :5; /* bit[29:25], SPI B MISO Input */
int SPIB_MOSI_I :5; /* bit[24:20], SPI B MOSI Input */
int SPI_CLK_I :5; /* bit[19:15], SPI Clock Input */
int SPI_DS_I :5; /* bit[14:10], SPI Device Select Input */
int SPI_MISO_I :5; /* bit[9:5], SPI MOSI Input */
int SPI_MOSI_I :5; /* bit[4:0], SPI MISO Input */
} BIT;
}ST_SRU2_INPUT0;

typedef union st_sru2_input1 /* SRU2_INPUT1 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int TWI_SCLK_I :5; /* bit[29:25], TWI Serial Clock Input */
int TWI_SDATA_I :5; /* bit[24:20], TWI Serial Data Input */
int UART1_RX_I :5; /* bit[19:15], UART 1 Receiver Input */
int UART0_RX_I :5; /* bit[14:10], UART 0 Receiver Input */
int SPIB_CLK_I :5; /* bit[9:5], SPI B Clock Input */
int SPIB_DS_I :5; /* bit[4:0], SPIB Device Select Input */
} BIT;
}ST_SRU2_INPUT1;

typedef union st_sru2_input2 /* SRU2_INPUT2 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int FLAG6_I :5; /* bit[29:25], Flag 6 Input */
int FLAG5_I :5; /* bit[24:20], Flag 5 Input */
int FLAG4_I :5; /* bit[19:15], Flag 4 Input */
int TIMER2_I :5; /* bit[14:10], Timer 2 Input */
int TIMER1_I :5; /* bit[9:5], Timer 1 Input */
int TIMER0_I :5; /* bit[4:0], Timer 0 Input */
} BIT;
}ST_SRU2_INPUT2;

typedef union st_sru2_input3 /* SRU2_INPUT3 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int FLAG12_I :5; /* bit[29:25], Flag 12 Input */
int FLAG11_I :5; /* bit[24:20], Flag 11 Input */
int FLAG10_I :5; /* bit[19:15], Flag 10 Input */
int FLAG9_I :5; /* bit[14:10], Flag 9 Input */
int FLAG8_I :5; /* bit[9:5], Flag 8 Input */
int FLAG7_I :5; /* bit[4:0], Flag 7 Input */
} BIT;
}ST_SRU2_INPUT3;

typedef union st_sru2_input4 /* SRU2_INPUT4 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int MISC2_I :5; /* bit[29:25], Miscellaneous 2 Input */
int MISC1_I :5; /* bit[24:20], Miscellaneous 1 Input */
int MISC0_I :5; /* bit[19:15], Miscellaneous 0 Input */
int FLAG15_I :5; /* bit[14:10], Flag 15 Input */
int FLAG14_I :5; /* bit[9:5], Flag 14 Input */
int FLAG13_I :5; /* bit[4:0], Flag 13 Input */
} BIT;
}ST_SRU2_INPUT4;

typedef union st_sru2_input5 /* SRU2_INPUT5 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int MISC8_I :5; /* bit[29:25], Miscellaneous 8 Input */
int MISC7_I :5; /* bit[24:20], Miscellaneous 7 Input */
int MISC6_I :5; /* bit[19:15], Miscellaneous 6 Input */
int MISC5_I :5; /* bit[14:10], Miscellaneous 5 Input */
int MISC4_I :5; /* bit[9:5], Miscellaneous 4 Input */
int MISC3_I :5; /* bit[4:0], Miscellaneous 3 Input */
} BIT;
}ST_SRU2_INPUT5;

typedef union st_sru2_pin0 /* SRU2_PIN0 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DPI_PB05_I :6; /* bit[29:24], DPI pin buffer 5 Input */
int DPI_PB04_I :6; /* bit[23:18], DPI pin buffer 4 Input */
int DPI_PB03_I :6; /* bit[17:12], DPI pin buffer 3 Input */
int DPI_PB02_I :6; /* bit[11:6], DPI pin buffer 2 Input */
int DPI_PB01_I :6; /* bit[5:0], DPI pin buffer 1 Input */
} BIT;
}ST_SRU2_PIN0;

typedef union st_sru2_pin1 /* SRU2_PIN1 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DPI_PB10_I :6; /* bit[29:24], DPI pin buffer 10 Input */
int DPI_PB09_I :6; /* bit[23:18], DPI pin buffer 9 Input */
int DPI_PB08_I :6; /* bit[17:12], DPI pin buffer 8 Input */
int DPI_PB07_I :6; /* bit[11:6], DPI pin buffer 7 Input */
int DPI_PB06_I :6; /* bit[5:0], DPI pin buffer 6 Input */
} BIT;
}ST_SRU2_PIN1;

typedef union st_sru2_pin2 /* SRU2_PIN2 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :8; /* bit[31:24], reserved */
int DPI_PB14_I :6; /* bit[23:18], DPI pin buffer 14 Input */
int DPI_PB13_I :6; /* bit[17:12], DPI pin buffer 13 Input */
int DPI_PB12_I :6; /* bit[11:6], DPI pin buffer 12 Input */
int DPI_PB11_I :6; /* bit[5:0], DPI pin buffer 11 Input */
} BIT;
}ST_SRU2_PIN2;

typedef union st_sru2_pben0 /* SRU2_PBEN0 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DPI_PBEN05_I :6; /* bit[29:24], DPI Pin Buffer Enable 5 Input */
int DPI_PBEN04_I :6; /* bit[23:18], DPI Pin Buffer Enable 4 Input */
int DPI_PBEN03_I :6; /* bit[17:12], DPI Pin Buffer Enable 3 Input */
int DPI_PBEN02_I :6; /* bit[11:6], DPI Pin Buffer Enable 2 Input */
int DPI_PBEN01_I :6; /* bit[5:0], DPI Pin Buffer Enable 1 Input */
} BIT;
}ST_SRU2_PBEN0;

typedef union st_sru2_pben1 /* SRU2_PBEN1 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int DPI_PBEN10_I :6; /* bit[29:24], DPI Pin Buffer Enable 10 Input */
int DPI_PBEN09_I :6; /* bit[23:18], DPI Pin Buffer Enable 9 Input */
int DPI_PBEN08_I :6; /* bit[17:12], DPI Pin Buffer Enable 8 Input */
int DPI_PBEN07_I :6; /* bit[11:6], DPI Pin Buffer Enable 7 Input */
int DPI_PBEN06_I :6; /* bit[5:0], DPI Pin Buffer Enable 6 Input */
} BIT;
}ST_SRU2_PBEN1;

typedef union st_sru2_pben2 /* SRU2_PBEN2 Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :8; /* bit[31:24], reserved */
int DPI_PBEN14_I :6; /* bit[23:18], DPI Pin Buffer Enable 14 Input */
int DPI_PBEN13_I :6; /* bit[17:12], DPI Pin Buffer Enable 13 Input */
int DPI_PBEN12_I :6; /* bit[11:6], DPI Pin Buffer Enable 12 Input */
int DPI_PBEN11_I :6; /* bit[5:0], DPI Pin Buffer Enable 11 Input */
} BIT;
}ST_SRU2_PBEN2;

//DPI Registers

typedef union st_dpi_pin_pullup /* DPI Resistor Pull-up Enable Register (DPI_PIN_PULLUP) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :18; /* bit[31:14], reserved */
int DPI_P14_PULLUP :1; /* bit[13], DPI Pin 14 Pullup Enable */
int DPI_P13_PULLUP :1; /* bit[12], DPI Pin 13 Pullup Enable */
int DPI_P12_PULLUP :1; /* bit[11], DPI Pin 12 Pullup Enable */
int DPI_P11_PULLUP :1; /* bit[10], DPI Pin 11 Pullup Enable */
int DPI_P10_PULLUP :1; /* bit[9], DPI Pin 10 Pullup Enable */
int DPI_P09_PULLUP :1; /* bit[8], DPI Pin 9 Pullup Enable */
int DPI_P08_PULLUP :1; /* bit[7], DPI Pin 8 Pullup Enable */
int DPI_P07_PULLUP :1; /* bit[6], DPI Pin 7 Pullup Enable */
int DPI_P06_PULLUP :1; /* bit[5], DPI Pin 6 Pullup Enable */
int DPI_P05_PULLUP :1; /* bit[4], DPI Pin 5 Pullup Enable */
int DPI_P04_PULLUP :1; /* bit[3], DPI Pin 4 Pullup Enable */
int DPI_P03_PULLUP :1; /* bit[2], DPI Pin 3 Pullup Enable */
int DPI_P02_PULLUP :1; /* bit[1], DPI Pin 2 Pullup Enable */
int DPI_P01_PULLUP :1; /* bit[0], DPI Pin 1 Pullup Enable */
} BIT;
}ST_DPI_PIN_PULLUP;

typedef union st_dpi_pin_stat /* DPI Pin Buffer Status Register (DPI_PIN_STAT) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :18; /* bit[31:14], reserved */
int DPI_PB14 :1; /* bit[13], DPI Pin 14 Status */
int DPI_PB13 :1; /* bit[12], DPI Pin 13 Status */
int DPI_PB12 :1; /* bit[11], DPI Pin 12 Status */
int DPI_PB11 :1; /* bit[10], DPI Pin 11 Status */
int DPI_PB10 :1; /* bit[9], DPI Pin 10 Status */
int DPI_PB09 :1; /* bit[8], DPI Pin 9 Status */
int DPI_PB08 :1; /* bit[7], DPI Pin 8 Status */
int DPI_PB07 :1; /* bit[6], DPI Pin 7 Status */
int DPI_PB06 :1; /* bit[5], DPI Pin 6 Status */
int DPI_PB05 :1; /* bit[4], DPI Pin 5 Status */
int DPI_PB04 :1; /* bit[3], DPI Pin 4 Status */
int DPI_PB03 :1; /* bit[2], DPI Pin 3 Status */
int DPI_PB02 :1; /* bit[1], DPI Pin 2 Status */
int DPI_PB01 :1; /* bit[0], DPI Pin 1 Status */
} BIT;
}ST_DPI_PIN_STAT;

typedef union st_dpi_irptl /* DPI Interrupt Latch Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :18; /* bit[31:14], reserved */
int EXT_MISC_8_INT :1; /* bit[13], External misc 8 interrupt */
int EXT_MISC_7_INT :1; /* bit[12], External misc 7 interrupt */
int EXT_MISC_6_INT :1; /* bit[11], External misc 6 interrupt */
int EXT_MISC_5_INT :1; /* bit[10], External misc 5 interrupt */
int EXT_MISC_4_INT :1; /* bit[9], External misc 4 interrupt */
int EXT_MISC_3_INT :1; /* bit[8], External misc 3 interrupt */
int EXT_MISC_2_INT :1; /* bit[7], External misc 2 interrupt */
int EXT_MISC_1_INT :1; /* bit[6], External misc 1 interrupt */
int EXT_MISC_0_INT :1; /* bit[5], External misc 0 interrupt */
int TWI_INT :1; /* bit[4], TWI Interrupt */
int UART1_RX_INT :1; /* bit[3], UART1 Rx Interrupt */
int UART0_RX_INT :1; /* bit[2], UART0 Rx Interrupt */
int UART1_TX_INT :1; /* bit[1], UART1 Tx Interrupt */
int UART0_TX_INT :1; /* bit[0], UART0 Tx Interrupt */
} BIT;
}ST_DPI_IRPTL;

//Precision Clock Control Registers
typedef union st_pcg_ctl0 /* Precision Clock A/B/C/D Control Register 0 */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int ENCLK :1; /* bit[31], Enable Clock */
int ENFS :1; /* bit[30], Enable Frame Sync */
int FS_PHASE_HI :10; /* bit[29:20], Phase HI for Frame Sync */
int FS_DIV :20; /* bit[19:0], Divisor for Frame Sync */
} BIT;
}ST_PCG_CTL0;

typedef union st_pcg_ctl1 /* Precision Clock A/B/C/D Control Register 1 */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int CLK_SOURCE :1; /* bit[31], Clock Source */
int FS_SOURCE :1; /* bit[30], Frame Sync Source */
int FS_PHASE_LO :10; /* bit[29:20], Phase Low for Frame Sync */
int CLK_DIV :20; /* bit[19:0], Divisor for Clock */
} BIT;
}ST_PCG_CTL1;

typedef union st_pcg_pw /* PCG Pulse Width Registers */
{
union
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int PWFSB :16; /* bit[31:16], Pulse Width Frame Sync B/D */
int PWFSA :16; /* bit[15:0], Pulse Width Frame Sync A/C */
} WORD;
} NORMAL_MODE;

union
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :14; /* bit[31:18], reserved */
int INVFSB :1; /* bit[17], Active Low Frame Sync B/D */
int STROBEB :1; /* bit[16], One Shot Frame Sync B/D */
int RSRVD1 :14; /* bit[15:2], reserved */
int INVFSA :1; /* bit[1], Active Low Frame Sync A/C */
int STROBEA :1; /* bit[0], One Shot Frame Sync A/C */
} BIT;
} BYPASS_MODE;
}ST_PCG_PW;

typedef union st_pcg_sync /* PCG Frame Synchronization Registers (PCG_SYNC) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :12; /* bit[31:20], reserved */
int FSB_SOURCE_IOP :1; /* bit[19], Enable frame sync B input source */
int CLKB_SOURCE_IOP :1; /* bit[18], Enable clock B input source */
int CLKB_SYNC :1; /* bit[17], Enable synchronization of clock B with external LRCLK */
int FSB_SYNC :1; /* bit[16], Enable synchronization of FSB with external LRCLK */
int RSRVD1 :12; /* bit[15:4], reserved */
int FSA_SOURCE_IOP :1; /* bit[3], Enable frame sync A input source */
int CLKA_SOURCE_IOP :1; /* bit[2], Enable clock A input source */
int CLKA_SYNC :1; /* bit[1], Enable synchronization of clock A with external LRCLK */
int FSA_SYNC :1; /* bit[0], Enable synchronization of FSA with external LRCLK */
} BIT;
}ST_PCG_SYNC;

typedef union st_pcg_sync2 /* PCG Frame Synchronization Register 2 (PCG_SYNC2) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :12; /* bit[31:20], reserved */
int FSD_SOURCE_IOP :1; /* bit[19], Enable frame sync D input source */
int CLKD_SOURCE_IOP :1; /* bit[18], Enable clock D input source */
int CLKD_SYNC :1; /* bit[17], Enable synchronization of clock D with external LRCLK */
int FSD_SYNC :1; /* bit[16], Enable synchronization of FSD with external LRCLK */
int RSRVD1 :12; /* bit[15:4], reserved */
int FSC_SOURCE_IOP :1; /* bit[3], Enable frame sync C input source */
int CLKC_SOURCE_IOP :1; /* bit[2], Enable clock C input source */
int CLKC_SYNC :1; /* bit[1], Enable synchronization of clock C with external LRCLK */
int FSC_SYNC :1; /* bit[0], Enable synchronization of FSC with external LRCLK */
} BIT;
}ST_PCG_SYNC2;

typedef union st_picr0 /* Peripheral Interrupt Priority0 Control Register (PICR0) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int P5I :5; /* bit[29:25], SPORT5 Interrupt Programmable Interrupt 5 */
int P4I :5; /* bit[24:20], SPORT3 Interrupt Programmable Interrupt 4 */
int P3I :5; /* bit[19:15], SPORT1 Interrupt Programmable Interrupt 3 */
int P2I :5; /* bit[14:10], SPORT2 General-Purpose IOP Timer0 Interrupt Programmable Interrupt 2 */
int P1I :5; /* bit[9:5], SPI Interrupt Programmable Interrupt 1 */
int P0I :5; /* bit[4:0], DAI High Priority Interrupt Programmable Interrupt 0 */
} BIT;
}ST_PICR0;

typedef union st_picr1 /* Peripheral Interrupt Priority1 Control Register (PICR1) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int P11I :5; /* bit[29:25], SPORT7 Interrupt Programmable Interrupt 11 */
int P10I :5; /* bit[24:20], General-Purpose I/O Timer1 Interrupt Programmable Interrupt 10 */
int P9I :5; /* bit[19:15], External Port DMA Channel 0 Interrupt Programmable Interrupt 9 */
int P8I :5; /* bit[14:10], SPORT4 Interrupt Programmable Interrupt 8 */
int P7I :5; /* bit[9:5], SPORT2 Interrupt Programmable Interrupt 7 */
int P6I :5; /* bit[4:0], SPORT0 Interrupt Programmable Interrupt 6 */
} BIT;
}ST_PICR1;

typedef union st_picr2 /* Peripheral Interrupt Priority2 Control Register (PICR2) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :2; /* bit[31:30], reserved */
int P17I :5; /* bit[29:25], General-Purpose I/O Timer1 Interrupt Programmable Interrupt 17 */
int P16I :5; /* bit[24:20], Memory-to-Memory Interrupt Programmable Interrupt 15 */
int P15I :5; /* bit[19:15], External Port DMA Channel 0 Interrupt Programmable Interrupt 9 */
int P14I :5; /* bit[14:10], DPI Interrupt Programmable Interrupt 14 */
int P13I :5; /* bit[9:5], External Port DMA Channel 1 Interrupt Programmable Interrupt 13 */
int P12I :5; /* bit[4:0], DAI Interrupt Low Programmable Interrupt 12 */
} BIT;
}ST_PICR2;

typedef union st_picr3 /* Peripheral Interrupt Priority3 Control Register (PICR3) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :27; /* bit[31:5], reserved */
int P18I :5; /* bit[4:0], SPI B Interrupt Programmable Interrupt 18 */
} BIT;
}ST_PICR3;

// MTM Registers
typedef union st_mtmctl /* Memory-to-Memory DMA Control Register */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int MTMDMA0ACT :1; /* bit[31], Memory Write DMA Status */
int MTMDMA1ACT :1; /* bit[30], Memory Read DMA Status */
int RSRVD0 :28; /* bit[29:2], reserved */
int MTMFLUSH :1; /* bit[1], 1=Flush the FIFO and reset the read/write pointers */
int MTMDEN :1; /* bit[0], MTM DMA Enable */
} BIT;
}ST_MTMCTL;

//PWM Registers
typedef union st_pwmgctl /* PWM Global Control Register (PWMGCTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :16; /* bit[31:16], reserved */
int PWM_SYNCDIS3 :1; /* bit[15], PWM Sync Group 3 Disable */
int PWM_SYNCEN3 :1; /* bit[14], PWM Sync Group 3 Enable */
int PWM_SYNCDIS2 :1; /* bit[13], PWM Sync Group 2 Disable */
int PWM_SYNCEN2 :1; /* bit[12], PWM Sync Group 2 Enable */
int PWM_SYNCDIS1 :1; /* bit[11], PWM Sync Group 1 Disable */
int PWM_SYNCEN1 :1; /* bit[10], PWM Sync Group 1 Enable */
int PWM_SYNCDIS0 :1; /* bit[9], PWM Sync Group 0 Disable */
int PWM_SYNCEN0 :1; /* bit[8], PWM Sync Group 0 Enable */
int PWM_DIS3 :1; /* bit[7], PWM Group 3 Disable */
int PWM_EN3 :1; /* bit[6], PWM Group 3 Enable */
int PWM_DIS2 :1; /* bit[5], PWM Group 2 Disable */
int PWM_EN2 :1; /* bit[4], PWM Group 2 Enable */
int PWM_DIS1 :1; /* bit[3], PWM Group 1 Disable */
int PWM_EN1 :1; /* bit[2], PWM Group 1 Enable */
int PWM_DIS0 :1; /* bit[1], PWM Group 0 Disable */
int PWM_EN0 :1; /* bit[0], PWM Group 0 Enable */
} BIT;
}ST_PWMGCTL;

typedef union st_pwmgstat /* PWM Global Status Register (PWMGSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int PWM_STAT3 :1; /* bit[3], PWM Group 3 Period Completion Status */
int PWM_STAT2 :1; /* bit[2], PWM Group 2 Period Completion Status */
int PWM_STAT1 :1; /* bit[1], PWM Group 1 Period Completion Status */
int PWM_STAT0 :1; /* bit[0], PWM Group 0 Period Completion Status */
} BIT;
}ST_PWMGSTAT;

typedef union st_pwmctl /* PWM Control Register (PWMCTLx) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :26; /* bit[31:6], reserved */
int PWM_IRQEN :1; /* bit[5], Enable PWM Interrupts */
int RSRVD1 :2; /* bit[4:3], reserved */
int PWM_UPDATE :1; /* bit[2], Update Mode */
int PWM_PAIR :1; /* bit[1], Pair Mode */
int PWM_ALIGN :1; /* bit[0], Align Mode */
} BIT;
}ST_PWMCTL;

typedef union st_pwmstat /* PWM Status Registers (PWMSTATx) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :29; /* bit[31:3], reserved */
int PWM_PAIRSTAT :1; /* bit[2], PWM Paired Mode Status */
int RSRVD1 :1; /* bit[1], reserved */
int PWM_PHASE :1; /* bit[0], PWM Phase Status */
} BIT;
}ST_PWMSTAT;

typedef union st_pwmseg /* PWM Output Disable Registers (PWMSEGx) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int PWM_AL :1; /* bit[3], Channel A Low Disable */
int PWM_AH :1; /* bit[2], Channel A High Disable */
int PWM_BL :1; /* bit[1], Channel B Low Disable */
int PWM_BH :1; /* bit[0], Channel B High Disable */
} BIT;
}ST_PWMSEG;

typedef union st_pwmpol /* PWM Polarity Select Registers (PWMPOLx) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int PWM_POL0BH :1; /* bit[7], Write to set channel B High Polarity 0 */
int PWM_POL1BH :1; /* bit[6], Write to set channel B High Polarity 1 */
int PWM_POL0BL :1; /* bit[5], Write to Set Channel B Low Polarity 0 */
int PWM_POL1BL :1; /* bit[4], Write to Set Channel B Low Polarity 1 */
int PWM_POL0AH :1; /* bit[3], Write to set channel A High Polarity 0 */
int PWM_POL1AH :1; /* bit[2], Write to set channel A High Polarity 1 */
int PWM_POL0AL :1; /* bit[1], Write to Set Channel A Low Polarity 0 */
int PWM_POL1AL :1; /* bit[0], Write to Set Channel A Low Polarity 1 */
} BIT;
}ST_PWMPOL;

//UART Registers
typedef union st_uartthr /* Transmit Hold Registers (UARTxTHR) */
{
union
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :23; /* bit[31:9], reserved */
int TX9D :1; /* bit[8], low byte Tx9 bit */
int BYTE :8; /* bit[7:0], data byte */
} BIT;
} NORMAL_MODE;

union
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :7; /* bit[31:25], reserved */
int TX9D1 :1; /* bit[24], high byte Tx9 bit */
int HI_BYTE :8; /* bit[23:16], high byte */
int RSRVD1 :7; /* bit[15:9], reserved */
int TX9D0 :1; /* bit[8], low byte Tx9 bit */
int LO_BYTE :8; /* bit[7:0], low byte */
} BIT;
} PACK_MODE;
}ST_UARTTHR;

typedef union st_uartrbr /* Receive Buffer Registers (UARTxRBR) */
{
union
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :23; /* bit[31:9], reserved */
int RX9D :1; /* bit[8], low byte Rx9 bit */
int BYTE :8; /* bit[7:0], data byte */
} BIT;
} NORMAL_MODE;

union
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSRVD0 :7; /* bit[31:25], reserved */
int RX9D1 :1; /* bit[24], high byte Rx9 bit */
int HI_BYTE :8; /* bit[23:16], high byte */
int RSRVD1 :7; /* bit[15:9], reserved */
int RX9D0 :1; /* bit[8], low byte Rx9 bit */
int LO_BYTE :8; /* bit[7:0], low byte */
} BIT;
} PACK_MODE;
}ST_UARTRBR;

typedef union st_uartier /* Interrupt Enable Registers (UARTxIER) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :27; /* bit[31:5], reserved */
int UARTADIE :1; /* bit[4], Enable Address Detect Interrupt in 9-Bit Mode */
int UARTTXFIE :1; /* bit[3], Enable Transmit Complete Interrupt */
int UARTLSIE :1; /* bit[2], Enable RX Status Interrupt */
int UARTTBEIE :1; /* bit[1], Enable Transmit Buffer Empty Interrupt */
int UARTRBFIE :1; /* bit[0], Enable Receive Buffer Full Interrupt */
} BIT;
}ST_UARTIER;

/*
In the order of interrupt priority, highest first.
011=Receive line status. Read UART_LSR to clear interrupt request.
100=Address detect. Read RBR to clear interrupt request.
010=Receive data ready. Read UART RBR to clear interrupt request.
001=UART_THR empty. Write UART_THR or read UART_IIR to clear interrupt request, when priority = 4.
000=UART THR & TSR empty (TEMT = transmit complete). Write UART_THR or read UART_IIR to clear interrupt request, when priority = 5 */
typedef union st_uartiir /* Interrupt Identification Registers (UARTxIIR) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int UARTISTAT :3; /* bit[3:1], UART Interrupt Status */
int UARTNOINT :1; /* bit[0], Pending Interrupt Status, 0=Interrupt pending */
/* 1=No interrupt pending */
} BIT;
}ST_UARTIIR;

typedef union st_uartlcr /* Line Control Registers (UARTxLCR) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int UARTDLAB :1; /* bit[7], Divisor Latch Access */
int UARTSB :1; /* bit[6], Set Break */
int UARTSTP :1; /* bit[5], Forces parity to defined value if set and PEN = 1 */
int UARTEPS :1; /* bit[4], Even Parity Select */
int UARTPEN :1; /* bit[3], Parity Enable */
int UARTSTB :1; /* bit[2], Stop Bits */
int UARTWLS :2; /* bit[1:0], Word Length Select */
} BIT;
}ST_UARTLCR;

typedef union st_uartmode /* Mode Registers (UARTxMODE) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :25; /* bit[31:7], reserved */
int UARTPST :2; /* bit[6:5], Pin Status */
int UARTAEN :1; /* bit[4], Enable Address Detect (if Rx9 = 1) */
int UARTRX9 :1; /* bit[3], Enable 9-Bit Tx in Receiver */
int UARTTX9 :1; /* bit[2], Enable 9-Bit Tx in Transmitter */
int UARTPKSYN :1; /* bit[1], Synchronize Data Packing in Rx */
int UARTPACK :1; /* bit[0], Packing Enable */
} BIT;
}ST_UARTMODE;

typedef union st_uartlsr /* Line Status Registers (UARTxLSR) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int UARTRX9D :1; /* bit[7], 9th bit of the received character-address detect */
int UARTTEMT :1; /* bit[6], TSR and UARTx_THR Empty */
int UARTTHRE :1; /* bit[5], UARTx_THR Empty */
int UARTBI :1; /* bit[4], Break Interrupt */
int UARTFE :1; /* bit[3], Framing Error */
int UARTPE :1; /* bit[2], Parity Error */
int UARTOE :1; /* bit[1], Overrun Error */
int UARTDR :1; /* bit[0], Data Ready */
} BIT;
}ST_UARTLSR;

typedef union st_uartctl /* DMA Control Registers (UARTxTXCTL, UARTxRXCTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :29; /* bit[31:3], reserved */
int UARTCHEN :1; /* bit[2], Chain Pointer DMA Enable */
int UARTDEN :1; /* bit[1], DMA Enable */
int UARTEN :1; /* bit[0], DMA Transmit Buffer Enable */
} BIT;
}ST_UARTCTL;

typedef union st_uarttxstat /* DMA Status Registers (UARTxTXSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :29; /* bit[31:3], reserved */
int UARTCHSTAT :1; /* bit[2], DMA Chaining Status */
int UARTDMASTAT :1; /* bit[1], DMA Status */
int RSRVD1 :1; /* bit[0], reserved */
} BIT;
}ST_UARTTXSTAT;

typedef union st_uartrxstat /* DMA Status Registers (UARTxRXSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :29; /* bit[31:3], reserved */
int UARTCHSTAT :1; /* bit[2], DMA Chaining Status */
int UARTDMASTAT :1; /* bit[1], DMA Status */
int UARTERRIRQ :1; /* bit[0], Receive Channel Error Interrupt */
} BIT;
}ST_UARTRXSTAT;

//TWI Registers
typedef union st_twidiv /* TWI Serial Clock Divider */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :16; /* bit[31:16], reserved */
int CLKHI :8; /* bit[15:8], value used to create the high durations of the serial clock (SCL) */
int CLKLOW :8; /* bit[7:0], value used to create the high durations of the serial clock (SCL) */
} BIT;
}ST_TWIDIV;

typedef union st_twisctl /* Slave Mode Control Register (TWISCTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :27; /* bit[31:5], reserved */
int TWIGCE :1; /* bit[4], General Call Enable */
int TWINAK :1; /* bit[3], Not Acknowledge */
int TWIDVAL :1; /* bit[2], Slave Transmit Data Valid */
int TWISLEN :1; /* bit[1], Slave Address Length */
int TWISEN :1; /* bit[0], Slave Enable */
} BIT;
}ST_TWISCTL;

typedef union st_twisstat /* Slave Status Register (TWISSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :30; /* bit[31:2], reserved */
int TWIGC :1; /* bit[1], General Call */
int TWISDIR :1; /* bit[0], Slave Transfer Direction */
} BIT;
}ST_TWISSTAT;

typedef union st_twimctl /* Master Control Register (TWIMCTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :16; /* bit[31:16], reserved */
int TWISCLOVR :1; /* bit[15], Serial Clock (SCL) Override */
int TWISDAOVR :1; /* bit[14], Serial Data (SDA) Override */
int TWIDCNT :8; /* bit[13:6], Data Transfer Count */
int TWIRSTART :1; /* bit[5], Repeat START */
int TWISTOP :1; /* bit[4], Issue STOP Condition */
int TWIFAST :1; /* bit[3], Fast Mode */
int TWIMDIR :1; /* bit[2], Master Transfer Direction */
int TWIMLEN :1; /* bit[1], Master Address Length */
int TWIMEN :1; /* bit[0], Master Mode Enable */
} BIT;
}ST_TWIMCTL;

typedef union st_twimstat /* Master Status Register (TWIMSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :23; /* bit[31:9], reserved */
int TWIBUSY :1; /* bit[8], Bus Busy */
int TWISCLSEN :1; /* bit[7], Serial Clock Sense */
int TWISDASEN :1; /* bit[6], Serial Data Sense */
int TWIWERR :1; /* bit[5], Buffer Write Error */
int TWIRERR :1; /* bit[4], Buffer Read Error */
int TWIDNAK :1; /* bit[3], Data Not Acknowledged */
int TWIANAK :1; /* bit[2], Address Not Acknowledged */
int TWILOST :1; /* bit[1], Lost Arbitration */
int TWIMPROG :1; /* bit[0], Master Tx in Progress */
} BIT;
}ST_TWIMSTAT;

typedef union st_twiirptl /* Interrupt Source Register (TWIIRPTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int TWIRXINT :1; /* bit[7], Receive FIFO Service */
int TWITXINT :1; /* bit[6], Transmit FIFO Service */
int TWIMERR :1; /* bit[5], Master Transfer Error */
int TWIMCOM :1; /* bit[4], Master Transfer Complete */
int TWISOVF :1; /* bit[3], Slave Overflow */
int TWISERR :1; /* bit[2], Slave Transfer Error */
int TWISCOMP :1; /* bit[1], Slave Transfer Complete */
int TWISINIT :1; /* bit[0], Slave Transfer Initiated */
} BIT;
}ST_TWIIRPTL;

typedef union st_twiimask /* Interrupt Enable Register (TWIIMASK) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int TWIRXINT :1; /* bit[7], Receive FIFO Service Interrupt Enable */
int TWITXINT :1; /* bit[6], Transmit FIFO Service Interrupt Enable */
int TWIMERR :1; /* bit[5], Master Transfer Error Interrupt Enable */
int TWIMCOM :1; /* bit[4], Master Transfer Complete Interrupt Enable */
int TWISOVF :1; /* bit[3], Slave Overflow Interrupt Enable */
int TWISERR :1; /* bit[2], Slave Transfer Error Interrupt Enable */
int TWISCOMP :1; /* bit[1], Slave Transfer Complete Interrupt Enable */
int TWISINIT :1; /* bit[0], Slave Transfer Initiated Interrupt Enable */
} BIT;
}ST_TWIIMASK;

typedef union st_twififoctl /* FIFO Control Register (TWIFIFOCTL) */
{
int ALL; /* All 16 bits */
struct
{
int :11; /* bit[15:5], reserved */
int _TWIBHD :1; /* bit[4], Buffer Hang Disable */
int _TWIRXINT2 :1; /* bit[3], Receive Buffer Interrupt Length */
int _TWITXINT2 :1; /* bit[2], Transmit Buffer Interrupt Length */
int _TWIRXFLUSH :1; /* bit[1], Receive Buffer Flush */
int _TWITXFLUSH :1; /* bit[0], Transmit Buffer Flush */
} BIT;
}ST_TWIFIFOCTL;

typedef union st_twififostat /* FIFO Status Register (TWIFIFOSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int TWIRXS :2; /* bit[3:2], Receive FIFO Status */
int TWITXS :2; /* bit[1:0], Transmit FIFO Status */
} BIT;
}ST_TWIFIFOSTAT;

typedef union st_twi16 /* 16-Bit Transmit/Receive FIFO Register (TXTWI16/RXTWI16) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :8; /* bit[31:24], reserved */
int BYTE1 :8; /* bit[23:16], Byte1-Transmitted second */
int RSRVD1 :8; /* bit[15:8], reserved */
int BYTE0 :8; /* bit[7:0], Byte0-Transmitted first */
} BIT;
}ST_TWI16;

// Sample Rate Converter registers

typedef union st_srcctl0 /* SRC Control Registers (SRCCTLx) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int SRC1_ENABLE :1; /* bit[31], SRC Enable */
int SRC1_MPHASE :1; /* bit[30], Match-Phase Mode Select */
int SRC1_LENOUT :2; /* bit[29:28], Output Word Length Select */
int SRC1_SMODEOUT :2; /* bit[27:26], Serial Output Format */
int SRC1_DITHER :1; /* bit[25], Dither Select */
int SRC1_SOFTMUTE :1; /* bit[24], Soft Mute */
int SRC1_DEEMPHASIS :2; /* bit[23:22], De-emphasis Filter Select */
int SRC1_BYPASS :1; /* bit[21], Bypass Mode Enable */
int SRC1_SMODEIN :3; /* bit[20:18], Serial Input Format */
int SRC1_AUTO_MUTE :1; /* bit[17], Auto Hard Mute */
int SRC1_HARD_MUTE :1; /* bit[16], Hard Mute */
int SRC0_ENABLE :1; /* bit[15], SRC0 Enable */
int SRC0_MPHASE :1; /* bit[14], Match-Phase Mode Select */
int SRC0_LENOUT :2; /* bit[13:12], Output Word Length Select */
int SRC0_SMODEOUT :2; /* bit[11:10], Serial Output Format */
int SRC0_DITHER :1; /* bit[9], Dither Select */
int SRC0_SOFTMUTE :1; /* bit[8], Soft Mute */
int SRC0_DEEMPHASIS :2; /* bit[7:6], De-emphasis Filter Select */
int SRC0_BYPASS :1; /* bit[5], Bypass SRC0 */
int SRC0_SMODEIN :3; /* bit[4:2], Serial Input Format */
int SRC0_AUTO_MUTE :1; /* bit[1], Auto Hard Mute */
int SRC0_HARD_MUTE :1; /* bit[0], Hard Mute */
} BIT;
}ST_SRCCTL0;

typedef union st_srcctl1 /* SRC Control Registers (SRCCTLx) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int SRC3_ENABLE :1; /* bit[31], SRC 3 Enable */
int SRC3_MPHASE :1; /* bit[30], Match-Phase Mode Select */
int SRC3_LENOUT :2; /* bit[29:28], Output Word Length Select */
int SRC3_SMODEOUT :2; /* bit[27:26], Serial Output Format */
int SRC3_DITHER :1; /* bit[25], Dither Select */
int SRC3_SOFTMUTE :1; /* bit[24], Soft Mute */
int SRC3_DEEMPHASIS :2; /* bit[23:22], De-emphasis Filter Select */
int SRC3_BYPASS :1; /* bit[21], Bypass Mode Enable */
int SRC3_SMODEIN :3; /* bit[20:18], Serial Input Format */
int SRC3_AUTO_MUTE :1; /* bit[17], Auto Hard Mute */
int SRC3_HARD_MUTE :1; /* bit[16], Hard Mute */
int SRC2_ENABLE :1; /* bit[15], SRC2 Enable */
int SRC2_MPHASE :1; /* bit[14], Match-Phase Mode Select */
int SRC2_LENOUT :2; /* bit[13:12], Output Word Length Select */
int SRC2_SMODEOUT :2; /* bit[11:10], Serial Output Format */
int SRC2_DITHER :1; /* bit[9], Dither Select */
int SRC2_SOFTMUTE :1; /* bit[8], Soft Mute */
int SRC2_DEEMPHASIS :2; /* bit[7:6], De-emphasis Filter Select */
int SRC2_BYPASS :1; /* bit[5], Bypass SRC2 */
int SRC2_SMODEIN :3; /* bit[4:2], Serial Input Format */
int SRC2_AUTO_MUTE :1; /* bit[1], Auto Hard Mute */
int SRC2_HARD_MUTE :1; /* bit[0], Hard Mute */
} BIT;
}ST_SRCCTL1;

typedef union st_srcmute /* SRC Mute Register (SRCMUTE) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :28; /* bit[31:4], reserved */
int SRC3_MUTE_EN :1; /* bit[3], SRC3 Mute Enable */
int SRC2_MUTE_EN :1; /* bit[2], SRC2 Mute Enable */
int SRC1_MUTE_EN :1; /* bit[1], SRC1 Mute Enable */
int SRC0_MUTE_EN :1; /* bit[0], SRC0 Mute Enable */
} BIT;
}ST_SRCMUTE;

typedef union st_srcrat0 /* SRC Ratio Registers (SRCRAT0) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int SRC1_MUTEOUT :1; /* bit[31], SRC1 Mute Output Enabled */
int SRC1_RATIO1 :15; /* bit[30:16], SRC1 Ratio Bit Field */
int SRC0_MUTEOUT :1; /* bit[15], SRC0 Mute Output Enabled */
int SRC0_RATIO1 :15; /* bit[14:0], SRC0 Ratio Bit Field */
} BIT;
}ST_SRCRAT0;

typedef union st_srcrat1 /* SRC Ratio Registers (SRCRAT1) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int SRC3_MUTEOUT :1; /* bit[31], SRC3 Mute Output Enabled */
int SRC3_RATIO1 :15; /* bit[30:16], SRC3 Ratio Bit Field */
int SRC2_MUTEOUT :1; /* bit[15], SRC2 Mute Output Enabled */
int SRC2_RATIO1 :15; /* bit[14:0], SRC2 Ratio Bit Field */
} BIT;
}ST_SRCRAT1;

typedef union st_ditctl /* Transmitter Control Register (DITCTL) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int DIT_B0CHANR :8; /* bit[31:24], Channel status byte 0 for subframe B */
int DIT_B0CHANL :8; /* bit[23:16], Channel status byte 0 for subframe A */
int DIT_EXT_SYNCEN :1; /* bit[15], External Sync Enable */
int RSRVD0 :1; /* bit[14], reserved */
int DIT_USERS :1; /* bit[13], User Bits Status */
int DIT_BLK_STAT :1; /* bit[12], Block Status (read-only) */
int DIT_VALIDR :1; /* bit[11], Validity Bit B */
int DIT_VALIDL :1; /* bit[10], Validity Bit A */
int DIT_STANDALONE_MODE :1; /* bit[9], Standalone Mode Enable */
int DIT_SMODEIN :3; /* bit[8:6], Serial Data Input Format */
int DIT_SCDF_LR :1; /* bit[5], Select single-channel, double-frequency mode channel */
int DIT_SCDF :1; /* bit[4], Transmit Single-Channel, Double-Frequency Enable */
int DIT_FREQ :2; /* bit[3:2], Frequency Multiplier */
int DIT_MUTE :1; /* bit[1], Mutes the serial data output */
int DIT_EN :1; /* bit[0], Transmitter Enable */
} BIT;
}ST_DITCTL;

typedef union st_ditchan0 /* Left Channel Status for Subframe A Register (DITCHANA0/B0) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE4 :8; /* bit[31:24], byte 4 */
int BYTE3 :8; /* bit[23:16], byte 3 */
int BYTE2 :8; /* bit[15:8], byte 2 */
int BYTE1 :8; /* bit[7:0], byte 1 */
} BYTE;
}ST_DITCHAN0;

typedef union st_ditchan1 /* Left Channel Status for Subframe A Register (DITCHANA1/B1) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE8 :8; /* bit[31:24], byte 8 */
int BYTE7 :8; /* bit[23:16], byte 7 */
int BYTE6 :8; /* bit[15:8], byte 6 */
int BYTE5 :8; /* bit[7:0], byte 5 */
} BYTE;
}ST_DITCHAN1;

typedef union st_ditchan2 /* Left Channel Status for Subframe A Register (DITCHANA2/B2) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE12 :8; /* bit[31:24], byte 12 */
int BYTE11 :8; /* bit[23:16], byte 11 */
int BYTE10 :8; /* bit[15:8], byte 10 */
int BYTE9 :8; /* bit[7:0], byte 9 */
} BYTE;
}ST_DITCHAN2;

typedef union st_ditchan3 /* Left Channel Status for Subframe A Register (DITCHANA3/B3) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE16 :8; /* bit[31:24], byte 16 */
int BYTE15 :8; /* bit[23:16], byte 15 */
int BYTE14 :8; /* bit[15:8], byte 14 */
int BYTE13 :8; /* bit[7:0], byte 13 */
} BYTE;
}ST_DITCHAN3;

typedef union st_ditchan4 /* Left Channel Status for Subframe A Register (DITCHANA4/B4) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE20 :8; /* bit[31:24], byte 20 */
int BYTE19 :8; /* bit[23:16], byte 19 */
int BYTE18 :8; /* bit[15:8], byte 18 */
int BYTE17 :8; /* bit[7:0], byte 17 */
} BYTE;
}ST_DITCHAN4;

typedef union st_ditchan5 /* Left Channel Status for Subframe A Register (DITCHANA5/B5) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int RSVD :8; /* bit[31:24], reserved */
int BYTE23 :8; /* bit[23:16], byte 23 */
int BYTE22 :8; /* bit[15:8], byte 22 */
int BYTE21 :8; /* bit[7:0], byte 21 */
} BYTE;
}ST_DITCHAN5;

typedef union st_ditusrbit0 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE3 :8; /* bit[31:24], byte 3 */
int BYTE2 :8; /* bit[23:16], byte 2 */
int BYTE1 :8; /* bit[15:8], byte 1 */
int BYTE0 :8; /* bit[7:0], byte 0 */
} BYTE;
}ST_DITUSRBIT0;

typedef union st_ditusrbit1 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE7 :8; /* bit[31:24], byte 7 */
int BYTE6 :8; /* bit[23:16], byte 6 */
int BYTE5 :8; /* bit[15:8], byte 5 */
int BYTE4 :8; /* bit[7:0], byte 4 */
} BYTE;
}ST_DITUSRBIT1;

typedef union st_ditusrbit2 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE11 :8; /* bit[31:24], byte 11 */
int BYTE10 :8; /* bit[23:16], byte 10 */
int BYTE9 :8; /* bit[15:8], byte 9 */
int BYTE8 :8; /* bit[7:0], byte 8 */
} BYTE;
}ST_DITUSRBIT2;

typedef union st_ditusrbit3 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE15 :8; /* bit[31:24], byte 15 */
int BYTE14 :8; /* bit[23:16], byte 14 */
int BYTE13 :8; /* bit[15:8], byte 13 */
int BYTE12 :8; /* bit[7:0], byte 12 */
} BYTE;
}ST_DITUSRBIT3;

typedef union st_ditusrbit4 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE19 :8; /* bit[31:24], byte 19 */
int BYTE18 :8; /* bit[23:16], byte 18 */
int BYTE17 :8; /* bit[15:8], byte 17 */
int BYTE16 :8; /* bit[7:0], byte 16 */
} BYTE;
}ST_DITUSRBIT4;

typedef union st_ditusrbit5 /* User Bits Buffer Registers for Subframe A/B Registers */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int BYTE23 :8; /* bit[31:24], byte 23 */
int BYTE22 :8; /* bit[23:16], byte 22 */
int BYTE21 :8; /* bit[15:8], byte 21 */
int BYTE20 :8; /* bit[7:0], byte 20 */
} BYTE;
}ST_DITUSRBIT5;

typedef union st_dirctl /* Receiver Control Register (DIRCTL) */
{
int ALL; /* All 32 bits */
struct
{
int RSRVD0 :24; /* bit[31:8], reserved */
int DIR_PLLDIS :1; /* bit[7], Disable PLL */
int DIR_MUTE :1; /* bit[6], Mute */
int DIR_SCDF :1; /* bit[5], Single-Channel, Double-Frequency Mode Enable */
int DIR_SCDF_LR :1; /* bit[4], Single-Channel, Double-Frequency Channel Select */
int DIR_LOCK :2; /* bit[3:2], Lock Error Control */
int DIR_BIPHASE :2; /* bit[1:0], Parity Biphase Error Control */
} BIT;
}ST_DIRCTL;

typedef union st_dirstat /* Receiver Status Register (DIRSTAT) */
{
int ALL; /* All 32 bits */
struct
{
int DIR_B0CHANR :8; /* bit[31:24], Channel Status Byte 0 for Subframe B */
int DIR_B0CHANL :8; /* bit[23:16], Channel Status Byte 0 for Subframe A */
int RSRVD0 :8; /* bit[15:8], reserved */
int DIR_BIPHASEERROR:1; /* bit[7], Biphase Error */
int DIR_PARITYERROR :1; /* bit[6], Indicates Parity Error */
int DIR_NOSTREAM :1; /* bit[5], Stream Disconnected */
int DIR_LOCK :1; /* bit[4], Lock Receiver */
int DIR_VALID :1; /* bit[3], Validity Bit. ORed Value of Channel 1 and 2 */
int DIR_NOAUDIOLR :1; /* bit[2], Non-Audio Subframe Mode Channel 1 and 2 */
int DIR_NOAUDIOR :1; /* bit[1], Non-Audio Subframe Mode Channel 2 */
int DIR_NOAUDIOL :1; /* bit[0], Non-Audio Subframe Mode Channel 1 */
} BIT;
}ST_DIRSTAT;

typedef union st_dirchanl /* Left Channel Status for Subframe A Register (DIRCHANL) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int DIR_B4CHANL :8; /* bit[31:24], Channel status byte 4 for subframe A */
int DIR_B3CHANL :8; /* bit[23:16], Channel status byte 3 for subframe A */
int DIR_B2CHANL :8; /* bit[15:8], Channel status byte 2 for subframe A */
int DIR_B1CHANL :8; /* bit[7:0], Channel status byte 1 for subframe A */
} BYTE;
}ST_DIRCHANL;

typedef union st_dirchanr /* Left Channel Status for Subframe B Register (DIRCHANR) */
{
int ALL; /* All 32 bits */
struct /* Word Access */
{
int H :16;
int L :16;
} WORD;
struct
{
int DIR_B4CHANR :8; /* bit[31:24], Channel status byte 4 for subframe R */
int DIR_B3CHANR :8; /* bit[23:16], Channel status byte 3 for subframe R */
int DIR_B2CHANR :8; /* bit[15:8], Channel status byte 2 for subframe R */
int DIR_B1CHANR :8; /* bit[7:0], Channel status byte 1 for subframe R */
} BYTE;
}ST_DIRCHANR;

//==============================================================================
//
// I/O Processor Register Address Memory Map
//
//==============================================================================

// Emulation/Breakpoint Registers
#define EEMUIN (*(volatile int *)0x30020) // Emulator Input FIFO
#define EEMUSTAT (*(volatile ST_EEMUSTAT *)0x30021) // Enhanced Emulation Status Register
#define EEMUOUT (*(volatile int *)0x30022) // Emulator Output FIFO
#define OSPID (*(volatile int *)0x30023) // Operating System Process ID
#define SYSCTL (*(volatile ST_SYSCTL *)0x30024) // System Control Register
#define BRKCTL (*(volatile ST_BRKCTL *)0x30025) // Hardware Breakpoint Control Register
#define REVPID (*(volatile int *)0x30026) // Emulation/Revision ID Register
#define PSA1S (*(volatile int *)0x300a0) // Instruction Breakpoint Address Start #1
#define PSA1E (*(volatile int *)0x300a1) // Instruction Breakpoint Address End #1
#define PSA2S (*(volatile int *)0x300a2) // Instruction Breakpoint Address Start #2
#define PSA2E (*(volatile int *)0x300a3) // Instruction Breakpoint Address End #2
#define PSA3S (*(volatile int *)0x300a4) // Instruction Breakpoint Address Start #3
#define PSA3E (*(volatile int *)0x300a5) // Instruction Breakpoint Address End #3
#define PSA4S (*(volatile int *)0x300a6) // Instruction Breakpoint Address Start #4
#define PSA4E (*(volatile int *)0x300a7) // Instruction Breakpoint Address End #4
#define DMA1S (*(volatile int *)0x300b2) // Data Memory Breakpoint Address Start #1
#define DMA1E (*(volatile int *)0x300b3) // Data Memory Breakpoint Address Start #1
#define DMA2S (*(volatile int *)0x300b4) // Data Memory Breakpoint Address Start #2
#define DMA2E (*(volatile int *)0x300b5) // Data Memory Breakpoint Address Start #2
#define D1IC (*(volatile int *)0x300b6)
#define D1ID (*(volatile int *)0x300b7)
#define PMDAS (*(volatile int *)0x300b8) // Program Memory Breakpoint Address Start #1
#define PMDAE (*(volatile int *)0x300b9) // Program Memory Breakpoint Address Start #1
#define D2IC (*(volatile int *)0x300bc)
#define D2ID (*(volatile int *)0x300bd)
#define EMUN (*(volatile int *)0x300ae) // Number of Breakpoints before EMU interrupt

// IOP registers for SDRAM controller
#define SDCTL (*(volatile ST_SDCTL *)0x1800) // SDRAM Control Register
#define EPCTL (*(volatile ST_EPCTL *)0x1801) // External Port Global Control Register
#define SDRRC (*(volatile ST_SDRRC *)0x1802) // SDRAM Refresh Rate Control Register
#define SDSTAT (*(volatile ST_SDSTAT *)0x1803) // SDRAM Status Register

#define BMAX (*(volatile int *)0x180d) // Bus time-out maximum
#define BCNT (*(volatile int *)0x180e) // Bus time-out counter
#define SYSTAT (*(volatile ST_SYSTAT *)0x180f) // System Shared Bus Status Register

#define AMICTL0 (*(volatile ST_AMICTL *)0x1804) // Asynchronous Memory Interface Control Register for Bank 1
#define AMICTL1 (*(volatile ST_AMICTL *)0x1805) // Asynchronous Memory Interface Control Register for Bank 2
#define AMICTL2 (*(volatile ST_AMICTL *)0x1806) // Asynchronous Memory Interface Control Register for Bank 3
#define AMICTL3 (*(volatile ST_AMICTL *)0x1807) // Asynchronous Memory Interface Control Register for Bank 4
#define AMISTAT (*(volatile ST_AMISTAT *)0x180a) // Asynchronous Memory Interface Status Register

//DMA address registers
#define DMAC0 (*(volatile ST_DMAC *)0x180b) // External Port DMA Channel 0 Control Register
#define DMAC1 (*(volatile ST_DMAC *)0x180c) // External Port DMA Channel 1 Control Register

#define EIEP0 (*(volatile int *)0x1820) // External Port DMA external index address
#define EMEP0 (*(volatile int *)0x1821) // External Port DMA external modifier
#define ECEP0 (*(volatile int *)0x1822) // External Port DMA external count
#define IIEP0 (*(volatile int *)0x1823) // External Port DMA internal index address
#define IMEP0 (*(volatile int *)0x1824) // External Port DMA internal modifier
#define ICEP0 (*(volatile int *)0x1825) // External Port DMA internal count
#define CEP0 (*(volatile int *)0x1825) // External Port DMA internal count
#define CPEP0 (*(volatile int *)0x1826) // External Port DMA chain pointer
#define EBEP0 (*(volatile int *)0x1827) // External Port DMA external base address
#define TPEP0 (*(volatile int *)0x1828) // External Port DMA tap pointer
#define ELEP0 (*(volatile int *)0x1829) // External Port DMA external length
#define DFEP0 (*(volatile int *)0x182c) // Data FIFO
#define TFEP0 (*(volatile int *)0x182d) // Tap List FIFO

#define EIEP1 (*(volatile int *)0x1830) // External Port DMA external index address
#define EMEP1 (*(volatile int *)0x1831) // External Port DMA external modifier
#define ECEP1 (*(volatile int *)0x1832) // External Port DMA external count
#define IIEP1 (*(volatile int *)0x1833) // External Port DMA internal index address
#define IMEP1 (*(volatile int *)0x1834) // External Port DMA internal modifier
#define ICEP1 (*(volatile int *)0x1835) // External Port DMA internal count
#define CEP1 (*(volatile int *)0x1835) // External Port DMA internal count
#define CPEP1 (*(volatile int *)0x1836) // External Port DMA chain pointer
#define EBEP1 (*(volatile int *)0x1837) // External Port DMA external base address
#define TPEP1 (*(volatile int *)0x1838) // External Port DMA tap pointer
#define ELEP1 (*(volatile int *)0x1839) // External Port DMA external length
#define DFEP1 (*(volatile int *)0x183c) // Data FIFO
#define TFEP1 (*(volatile int *)0x183d) // Tap List FIFO

// SPORT
#define SPERRSTAT (*(volatile ST_SPERRSTAT *)0x2300) // SPORT Global Interrupt Status Register

// Serial Port registers (SP01)
#define SPCTL0 (*(volatile ST_SPCTL *)0xc00) // SPORT 0 control register
#define SPCTL1 (*(volatile ST_SPCTL *)0xc01) // SPORT 1 control register
#define DIV0 (*(volatile ST_DIV *)0xc02) // SPORT 0 divisor for transmit/receive SCLK0 and FS0
#define DIV1 (*(volatile ST_DIV *)0xc03) // SPORT 1 divisor for transmit/receive SCLK1 and FS1
#define SPMCTL0 (*(volatile ST_SPMCTL *)0xc04) // SPORT 0 Multichannel Control Register

// MT and MR registers are included here for code compatibility
#define MT0CS0 (*(volatile int *)0xc05) // SPORT 0 multichannel tx select, channels 31 - 0
#define MT0CS1 (*(volatile int *)0xc06) // SPORT 0 multichannel tx select, channels 63 - 32
#define MT0CS2 (*(volatile int *)0xc07) // SPORT 0 multichannel tx select, channels 95 - 64
#define MT0CS3 (*(volatile int *)0xc08) // SPORT 0 multichannel tx select, channels 127 - 96
#define MR1CS0 (*(volatile int *)0xc09) // SPORT 1 multichannel rx select, channels 31 - 0
#define MR1CS1 (*(volatile int *)0xc0A) // SPORT 1 multichannel rx select, channels 63 - 32
#define MR1CS2 (*(volatile int *)0xc0B) // SPORT 1 multichannel rx select, channels 95 - 64
#define MR1CS3 (*(volatile int *)0xc0C) // SPORT 1 multichannel rx select, channels 127 - 96
#define MT0CCS0 (*(volatile int *)0xc0D) // SPORT 0 multichannel tx compand select, channels 31 - 0
#define MT0CCS1 (*(volatile int *)0xc0E) // SPORT 0 multichannel tx compand select, channels 63 - 32
#define MT0CCS2 (*(volatile int *)0xc0F) // SPORT 0 multichannel tx compand select, channels 95 - 64
#define MT0CCS3 (*(volatile int *)0xc10) // SPORT 0 multichannel tx compand select, channels 127 - 96
#define MR1CCS0 (*(volatile int *)0xc11) // SPORT 1 multichannel rx compand select, channels 31 - 0
#define MR1CCS1 (*(volatile int *)0xc12) // SPORT 1 multichannel rx compand select, channels 63 - 32
#define MR1CCS2 (*(volatile int *)0xc13) // SPORT 1 multichannel rx compand select, channels 95 - 64
#define MR1CCS3 (*(volatile int *)0xc14) // SPORT 1 multichannel rx compand select, channels 127 - 96

#define SPCNT0 (*(volatile int *)0xc15) // SPORT Count register - status information for internal clock and fs
#define SPCNT1 (*(volatile int *)0xc16) // SPORT Count register - status information for internal clock and fs
#define SPMCTL1 (*(volatile ST_SPMCTL *)0xc17) // SPORT 1 Multichannel Control Register
#define SPERRCTL0 (*(volatile ST_SPERRCTL *)0xc18) // SPORT 0 Error Interrupt Control Register
#define SPERRCTL1 (*(volatile ST_SPERRCTL *)0xc19) // SPORT 1 Error Interrupt Control Register

// SPORT TDM registers - Naming changed since the direction is programmable now
#define SP0CS0 (*(volatile int *)0xc05) // SPORT 0 multichannel select, channels 31 - 0
#define SP0CS1 (*(volatile int *)0xc06) // SPORT 0 multichannel select, channels 63 - 32
#define SP0CS2 (*(volatile int *)0xc07) // SPORT 0 multichannel select, channels 95 - 64
#define SP0CS3 (*(volatile int *)0xc08) // SPORT 0 multichannel select, channels 127 - 96
#define SP1CS0 (*(volatile int *)0xc09) // SPORT 1 multichannel select, channels 31 - 0
#define SP1CS1 (*(volatile int *)0xc0A) // SPORT 1 multichannel select, channels 63 - 32
#define SP1CS2 (*(volatile int *)0xc0B) // SPORT 1 multichannel select, channels 95 - 64
#define SP1CS3 (*(volatile int *)0xc0C) // SPORT 1 multichannel select, channels 127 - 96
#define SP0CCS0 (*(volatile int *)0xc0D) // SPORT 0 multichannel compand select, channels 31 - 0
#define SP0CCS1 (*(volatile int *)0xc0E) // SPORT 0 multichannel compand select, channels 63 - 32
#define SP0CCS2 (*(volatile int *)0xc0F) // SPORT 0 multichannel compand select, channels 95 - 64
#define SP0CCS3 (*(volatile int *)0xc10) // SPORT 0 multichannel compand select, channels 127 - 96
#define SP1CCS0 (*(volatile int *)0xc11) // SPORT 1 multichannel compand select, channels 31 - 0
#define SP1CCS1 (*(volatile int *)0xc12) // SPORT 1 multichannel compand select, channels 63 - 32
#define SP1CCS2 (*(volatile int *)0xc13) // SPORT 1 multichannel compand select, channels 95 - 64
#define SP1CCS3 (*(volatile int *)0xc14) // SPORT 1 multichannel compand select, channels 127 - 96

#define IISP0A (*(volatile int *)0xc40) // Internal memory DMA address
#define IMSP0A (*(volatile int *)0xc41) // Internal memory DMA access modifier
#define CSP0A (*(volatile int *)0xc42) // Contains number of DMA transfers remaining
#define CPSP0A (*(volatile int *)0xc43) // Points to next DMA parameters
#define IISP0B (*(volatile int *)0xc44) // Internal memory DMA address
#define IMSP0B (*(volatile int *)0xc45) // Internal memory DMA access modifier
#define CSP0B (*(volatile int *)0xc46) // Contains number of DMA transfers remaining
#define CPSP0B (*(volatile int *)0xc47) // Points to next DMA parameters
#define IISP1A (*(volatile int *)0xc48) // Internal memory DMA address
#define IMSP1A (*(volatile int *)0xc49) // Internal memory DMA access modifier
#define CSP1A (*(volatile int *)0xc4A) // Contains number of DMA transfers remaining
#define CPSP1A (*(volatile int *)0xc4B) // Points to next DMA parameters
#define IISP1B (*(volatile int *)0xc4C) // Internal memory DMA address
#define IMSP1B (*(volatile int *)0xc4D) // Internal memory DMA access modifier
#define CSP1B (*(volatile int *)0xc4E) // Contains number of DMA transfers remaining
#define CPSP1B (*(volatile int *)0xc4F) // Points to next DMA parameters
#define TXSP0A (*(volatile int *)0xc60) // SPORT 0A transmit data register
#define RXSP0A (*(volatile int *)0xc61) // SPORT 0A receive data register
#define TXSP0B (*(volatile int *)0xc62) // SPORT 0B transmit data register
#define RXSP0B (*(volatile int *)0xc63) // SPORT 0B receive data register
#define TXSP1A (*(volatile int *)0xc64) // SPORT 1A transmit data register
#define RXSP1A (*(volatile int *)0xc65) // SPORT 1A receive data register
#define TXSP1B (*(volatile int *)0xc66) // SPORT 1B transmit data register
#define RXSP1B (*(volatile int *)0xc67) // SPORT 1B receive data register

// Serial Port registers (SP23)
#define SPCTL2 (*(volatile ST_SPCTL *)0x400) // SPORT 2 control register
#define SPCTL3 (*(volatile ST_SPCTL *)0x401) // SPORT 3 control register
#define DIV2 (*(volatile ST_DIV *)0x402) // SPORT 2 divisor for transmit/receive SCLK2 and FS2
#define DIV3 (*(volatile ST_DIV *)0x403) // SPORT 3 divisor for transmit/receive SCLK3 and FS3
#define SPMCTL2 (*(volatile ST_SPMCTL *)0x404) // SPORT 2 Multichannel Control Register

// MT and MR registers are included here for code compatibility
#define MT2CS0 (*(volatile int *)0x405) // SPORT 2 multichannel tx select, channels 31 - 0
#define MT2CS1 (*(volatile int *)0x406) // SPORT 2 multichannel tx select, channels 63 - 32
#define MT2CS2 (*(volatile int *)0x407) // SPORT 2 multichannel tx select, channels 95 - 64
#define MT2CS3 (*(volatile int *)0x408) // SPORT 2 multichannel tx select, channels 127 - 96
#define MR3CS0 (*(volatile int *)0x409) // SPORT 3 multichannel rx select, channels 31 - 0
#define MR3CS1 (*(volatile int *)0x40A) // SPORT 3 multichannel rx select, channels 63 - 32
#define MR3CS2 (*(volatile int *)0x40B) // SPORT 3 multichannel rx select, channels 95 - 64
#define MR3CS3 (*(volatile int *)0x40C) // SPORT 3 multichannel rx select, channels 127 - 96
#define MT2CCS0 (*(volatile int *)0x40D) // SPORT 2 multichannel tx compand select, channels 31 - 0
#define MT2CCS1 (*(volatile int *)0x40E) // SPORT 2 multichannel tx compand select, channels 63 - 32
#define MT2CCS2 (*(volatile int *)0x40F) // SPORT 2 multichannel tx compand select, channels 95 - 64
#define MT2CCS3 (*(volatile int *)0x410) // SPORT 2 multichannel tx compand select, channels 127 - 96
#define MR3CCS0 (*(volatile int *)0x411) // SPORT 3 multichannel rx compand select, channels 31 - 0
#define MR3CCS1 (*(volatile int *)0x412) // SPORT 3 multichannel rx compand select, channels 63 - 32
#define MR3CCS2 (*(volatile int *)0x413) // SPORT 3 multichannel rx compand select, channels 95 - 64
#define MR3CCS3 (*(volatile int *)0x414) // SPORT 3 multichannel rx compand select, channels 127 - 96

#define SPCNT2 (*(volatile int *)0x415) // SPORT Count register - status information for internal clock and fs
#define SPCNT3 (*(volatile int *)0x416) // SPORT Count register - status information for internal clock and fs
#define SPMCTL3 (*(volatile ST_SPMCTL *)0x417) // SPORT 3 Multichannel Control Register
#define SPERRCTL2 (*(volatile ST_SPERRCTL *)0x418) // SPORT 2 Error Interrupt Control Register
#define SPERRCTL3 (*(volatile ST_SPERRCTL *)0x419) // SPORT 3 Error Interrupt Control Register

// SPORT TDM registers - Naming changed since the direction is programmable now
#define SP2CS0 (*(volatile int *)0x405) // SPORT 2 multichannel select, channels 31 - 0
#define SP2CS1 (*(volatile int *)0x406) // SPORT 2 multichannel select, channels 63 - 32
#define SP2CS2 (*(volatile int *)0x407) // SPORT 2 multichannel select, channels 95 - 64
#define SP2CS3 (*(volatile int *)0x408) // SPORT 2 multichannel select, channels 127 - 96
#define SP3CS0 (*(volatile int *)0x409) // SPORT 3 multichannel select, channels 31 - 0
#define SP3CS1 (*(volatile int *)0x40A) // SPORT 3 multichannel select, channels 63 - 32
#define SP3CS2 (*(volatile int *)0x40B) // SPORT 3 multichannel select, channels 95 - 64
#define SP3CS3 (*(volatile int *)0x40C) // SPORT 3 multichannel select, channels 127 - 96
#define SP2CCS0 (*(volatile int *)0x40D) // SPORT 2 multichannel compand select, channels 31 - 0
#define SP2CCS1 (*(volatile int *)0x40E) // SPORT 2 multichannel compand select, channels 63 - 32
#define SP2CCS2 (*(volatile int *)0x40F) // SPORT 2 multichannel compand select, channels 95 - 64
#define SP2CCS3 (*(volatile int *)0x410) // SPORT 2 multichannel compand select, channels 127 - 96
#define SP3CCS0 (*(volatile int *)0x411) // SPORT 3 multichannel compand select, channels 31 - 0
#define SP3CCS1 (*(volatile int *)0x412) // SPORT 3 multichannel compand select, channels 63 - 32
#define SP3CCS2 (*(volatile int *)0x413) // SPORT 3 multichannel compand select, channels 95 - 64
#define SP3CCS3 (*(volatile int *)0x414) // SPORT 3 multichannel compand select, channels 127 - 96

#define IISP2A (*(volatile int *)0x440) // Internal memory DMA address
#define IMSP2A (*(volatile int *)0x441) // Internal memory DMA access modifier
#define CSP2A (*(volatile int *)0x442) // Contains number of DMA transfers remaining
#define CPSP2A (*(volatile int *)0x443) // Points to next DMA parameters
#define IISP2B (*(volatile int *)0x444) // Internal memory DMA address
#define IMSP2B (*(volatile int *)0x445) // Internal memory DMA access modifier
#define CSP2B (*(volatile int *)0x446) // Contains number of DMA transfers remaining
#define CPSP2B (*(volatile int *)0x447) // Points to next DMA parameters
#define IISP3A (*(volatile int *)0x448) // Internal memory DMA address
#define IMSP3A (*(volatile int *)0x449) // Internal memory DMA access modifier
#define CSP3A (*(volatile int *)0x44A) // Contains number of DMA transfers remaining
#define CPSP3A (*(volatile int *)0x44B) // Points to next DMA parameters
#define IISP3B (*(volatile int *)0x44C) // Internal memory DMA address
#define IMSP3B (*(volatile int *)0x44D) // Internal memory DMA access modifier
#define CSP3B (*(volatile int *)0x44E) // Contains number of DMA transfers remaining
#define CPSP3B (*(volatile int *)0x44F) // Points to next DMA parameters
#define TXSP2A (*(volatile int *)0x460) // SPORT 2A transmit data register
#define RXSP2A (*(volatile int *)0x461) // SPORT 2A receive data register
#define TXSP2B (*(volatile int *)0x462) // SPORT 2B transmit data register
#define RXSP2B (*(volatile int *)0x463) // SPORT 2B receive data register
#define TXSP3A (*(volatile int *)0x464) // SPORT 3A transmit data register
#define RXSP3A (*(volatile int *)0x465) // SPORT 3A receive data register
#define TXSP3B (*(volatile int *)0x466) // SPORT 3B transmit data register
#define RXSP3B (*(volatile int *)0x467) // SPORT 3B receive data register

// Serial Port registers (SP45)
#define SPCTL4 (*(volatile ST_SPCTL *)0x800) // SPORT 4 control register
#define SPCTL5 (*(volatile ST_SPCTL *)0x801) // SPORT 5 control register
#define DIV4 (*(volatile ST_DIV *)0x802) // SPORT 4 divisor for transmit/receive SCLK4 and FS4
#define DIV5 (*(volatile ST_DIV *)0x803) // SPORT 5 divisor for transmit/receive SCLK5 and FS5
#define SPMCTL4 (*(volatile ST_SPMCTL *)0x804) // SPORT 4 Multichannel Control Register

// MT and MR registers are included here for code compatibility
#define MT4CS0 (*(volatile int *)0x805) // SPORT 4 multichannel tx select, channels 31 - 0
#define MT4CS1 (*(volatile int *)0x806) // SPORT 4 multichannel tx select, channels 63 - 32
#define MT4CS2 (*(volatile int *)0x807) // SPORT 4 multichannel tx select, channels 95 - 64
#define MT4CS3 (*(volatile int *)0x808) // SPORT 4 multichannel tx select, channels 127 - 96
#define MR5CS0 (*(volatile int *)0x809) // SPORT 5 multichannel rx select, channels 31 - 0
#define MR5CS1 (*(volatile int *)0x80A) // SPORT 5 multichannel rx select, channels 63 - 32
#define MR5CS2 (*(volatile int *)0x80B) // SPORT 5 multichannel rx select, channels 95 - 64
#define MR5CS3 (*(volatile int *)0x80C) // SPORT 5 multichannel rx select, channels 127 - 96
#define MT4CCS0 (*(volatile int *)0x80D) // SPORT 4 multichannel tx compand select, channels 31 - 0
#define MT4CCS1 (*(volatile int *)0x80E) // SPORT 4 multichannel tx compand select, channels 63 - 32
#define MT4CCS2 (*(volatile int *)0x80F) // SPORT 4 multichannel tx compand select, channels 95 - 64
#define MT4CCS3 (*(volatile int *)0x810) // SPORT 4 multichannel tx compand select, channels 127 - 96
#define MR5CCS0 (*(volatile int *)0x811) // SPORT 5 multichannel rx compand select, channels 31 - 0
#define MR5CCS1 (*(volatile int *)0x812) // SPORT 5 multichannel rx compand select, channels 63 - 32
#define MR5CCS2 (*(volatile int *)0x813) // SPORT 5 multichannel rx compand select, channels 95 - 64
#define MR5CCS3 (*(volatile int *)0x814) // SPORT 5 multichannel rx compand select, channels 127 - 96

#define SPCNT4 (*(volatile int *)0x815) // SPORT Count register - status information for internal clock and fs
#define SPCNT5 (*(volatile int *)0x816) // SPORT Count register - status information for internal clock and fs
#define SPMCTL5 (*(volatile ST_SPMCTL *)0x817) // SPORT 5 Multichannel Control Register
#define SPERRCTL4 (*(volatile ST_SPERRCTL *)0x818) // SPORT 4 Error Interrupt Control Register
#define SPERRCTL5 (*(volatile ST_SPERRCTL *)0x819) // SPORT 5 Error Interrupt Control Register

// SPORT TDM registers - Naming changed since the direction is programmable now
#define SP4CS0 (*(volatile int *)0x805) // SPORT 4 multichannel select, channels 31 - 0
#define SP4CS1 (*(volatile int *)0x806) // SPORT 4 multichannel select, channels 63 - 32
#define SP4CS2 (*(volatile int *)0x807) // SPORT 4 multichannel select, channels 95 - 64
#define SP4CS3 (*(volatile int *)0x808) // SPORT 4 multichannel select, channels 127 - 96
#define SP5CS0 (*(volatile int *)0x809) // SPORT 5 multichannel select, channels 31 - 0
#define SP5CS1 (*(volatile int *)0x80A) // SPORT 5 multichannel select, channels 63 - 32
#define SP5CS2 (*(volatile int *)0x80B) // SPORT 5 multichannel select, channels 95 - 64
#define SP5CS3 (*(volatile int *)0x80C) // SPORT 5 multichannel select, channels 127 - 96
#define SP4CCS0 (*(volatile int *)0x80D) // SPORT 4 multichannel compand select, channels 31 - 0
#define SP4CCS1 (*(volatile int *)0x80E) // SPORT 4 multichannel compand select, channels 63 - 32
#define SP4CCS2 (*(volatile int *)0x80F) // SPORT 4 multichannel compand select, channels 95 - 64
#define SP4CCS3 (*(volatile int *)0x810) // SPORT 4 multichannel compand select, channels 127 - 96
#define SP5CCS0 (*(volatile int *)0x811) // SPORT 5 multichannel compand select, channels 31 - 0
#define SP5CCS1 (*(volatile int *)0x812) // SPORT 5 multichannel compand select, channels 63 - 32
#define SP5CCS2 (*(volatile int *)0x813) // SPORT 5 multichannel compand select, channels 95 - 64
#define SP5CCS3 (*(volatile int *)0x814) // SPORT 5 multichannel compand select, channels 127 - 96

#define IISP4A (*(volatile int *)0x840) // Internal memory DMA address
#define IMSP4A (*(volatile int *)0x841) // Internal memory DMA access modifier
#define CSP4A (*(volatile int *)0x842) // Contains number of DMA transfers remaining
#define CPSP4A (*(volatile int *)0x843) // Points to next DMA parameters
#define IISP4B (*(volatile int *)0x844) // Internal memory DMA address
#define IMSP4B (*(volatile int *)0x845) // Internal memory DMA access modifier
#define CSP4B (*(volatile int *)0x846) // Contains number of DMA transfers remaining
#define CPSP4B (*(volatile int *)0x847) // Points to next DMA parameters
#define IISP5A (*(volatile int *)0x848) // Internal memory DMA address
#define IMSP5A (*(volatile int *)0x849) // Internal memory DMA access modifier
#define CSP5A (*(volatile int *)0x84A) // Contains number of DMA transfers remaining
#define CPSP5A (*(volatile int *)0x84B) // Points to next DMA parameters
#define IISP5B (*(volatile int *)0x84C) // Internal memory DMA address
#define IMSP5B (*(volatile int *)0x84D) // Internal memory DMA access modifier
#define CSP5B (*(volatile int *)0x84E) // Contains number of DMA transfers remaining
#define CPSP5B (*(volatile int *)0x84F) // Points to next DMA parameters
#define TXSP4A (*(volatile int *)0x860) // SPORT 4A transmit data register
#define RXSP4A (*(volatile int *)0x861) // SPORT 4A receive data register
#define TXSP4B (*(volatile int *)0x862) // SPORT 4B transmit data register
#define RXSP4B (*(volatile int *)0x863) // SPORT 4B receive data register
#define TXSP5A (*(volatile int *)0x864) // SPORT 5A transmit data register
#define RXSP5A (*(volatile int *)0x865) // SPORT 5A receive data register
#define TXSP5B (*(volatile int *)0x866) // SPORT 5B transmit data register
#define RXSP5B (*(volatile int *)0x867) // SPORT 5B receive data register

// SP67
#define SPCTL6 (*(volatile ST_SPCTL *)0x4800) // SPORT 6 control register
#define SPCTL7 (*(volatile ST_SPCTL *)0x4801) // SPORT 7 control register
#define DIV6 (*(volatile ST_DIV *)0x4802) // SPORT 6 divisor for transmit/receive SCLK4 and FS4
#define DIV7 (*(volatile ST_DIV *)0x4803) // SPORT 7 divisor for transmit/receive SCLK5 and FS5
#define SPMCTL6 (*(volatile ST_SPMCTL *)0x4804) // SPORT 6 Multichannel Control Register

// MT and MR registers are included here for code compatibility
#define MT6CS0 (*(volatile int *)0x4805) // SPORT 6 multichannel tx select, channels 31 - 0
#define MT6CS1 (*(volatile int *)0x4806) // SPORT 6 multichannel tx select, channels 63 - 32
#define MT6CS2 (*(volatile int *)0x4807) // SPORT 6 multichannel tx select, channels 95 - 64
#define MT6CS3 (*(volatile int *)0x4808) // SPORT 6 multichannel tx select, channels 127 - 96
#define MR7CS0 (*(volatile int *)0x4809) // SPORT 7 multichannel rx select, channels 31 - 0
#define MR7CS1 (*(volatile int *)0x480A) // SPORT 7 multichannel rx select, channels 63 - 32
#define MR7CS2 (*(volatile int *)0x480B) // SPORT 7 multichannel rx select, channels 95 - 64
#define MR7CS3 (*(volatile int *)0x480C) // SPORT 7 multichannel rx select, channels 127 - 96
#define MT6CCS0 (*(volatile int *)0x480D) // SPORT 6 multichannel tx compand select, channels 31 - 0
#define MT6CCS1 (*(volatile int *)0x480E) // SPORT 6 multichannel tx compand select, channels 63 - 32
#define MT6CCS2 (*(volatile int *)0x480F) // SPORT 6 multichannel tx compand select, channels 95 - 64
#define MT6CCS3 (*(volatile int *)0x4810) // SPORT 6 multichannel tx compand select, channels 127 - 96
#define MR7CCS0 (*(volatile int *)0x4811) // SPORT 7 multichannel rx compand select, channels 31 - 0
#define MR7CCS1 (*(volatile int *)0x4812) // SPORT 7 multichannel rx compand select, channels 63 - 32
#define MR7CCS2 (*(volatile int *)0x4813) // SPORT 7 multichannel rx compand select, channels 95 - 64
#define MR7CCS3 (*(volatile int *)0x4814) // SPORT 7 multichannel rx compand select, channels 127 - 96

#define SPCNT6 (*(volatile int *)0x4815) // SPORT Count register - status information for internal clock and fs
#define SPCNT7 (*(volatile int *)0x4816) // SPORT Count register - status information for internal clock and fs
#define SPMCTL7 (*(volatile ST_SPMCTL *)0x4817) // SPORT 7 Multichannel Control Register
#define SPERRCTL6 (*(volatile ST_SPERRCTL *)0x4818) // SPORT 6 Error Interrupt Control Register
#define SPERRCTL7 (*(volatile ST_SPERRCTL *)0x4819) // SPORT 7 Error Interrupt Control Register

// SPORT TDM registers - Naming changed since the direction is programmable now
#define SP6CS0 (*(volatile int *)0x4805) // SPORT 6 multichannel select, channels 31 - 0
#define SP6CS1 (*(volatile int *)0x4806) // SPORT 6 multichannel select, channels 63 - 32
#define SP6CS2 (*(volatile int *)0x4807) // SPORT 6 multichannel select, channels 95 - 64
#define SP6CS3 (*(volatile int *)0x4808) // SPORT 6 multichannel select, channels 127 - 96
#define SP7CS0 (*(volatile int *)0x4809) // SPORT 7 multichannel select, channels 31 - 0
#define SP7CS1 (*(volatile int *)0x480A) // SPORT 7 multichannel select, channels 63 - 32
#define SP7CS2 (*(volatile int *)0x480B) // SPORT 7 multichannel select, channels 95 - 64
#define SP7CS3 (*(volatile int *)0x480C) // SPORT 7 multichannel select, channels 127 - 96
#define SP6CCS0 (*(volatile int *)0x480D) // SPORT 6 multichannel compand select, channels 31 - 0
#define SP6CCS1 (*(volatile int *)0x480E) // SPORT 6 multichannel compand select, channels 63 - 32
#define SP6CCS2 (*(volatile int *)0x480F) // SPORT 6 multichannel compand select, channels 95 - 64
#define SP6CCS3 (*(volatile int *)0x4810) // SPORT 6 multichannel compand select, channels 127 - 96
#define SP7CCS0 (*(volatile int *)0x4811) // SPORT 7 multichannel compand select, channels 31 - 0
#define SP7CCS1 (*(volatile int *)0x4812) // SPORT 7 multichannel compand select, channels 63 - 32
#define SP7CCS2 (*(volatile int *)0x4813) // SPORT 7 multichannel compand select, channels 95 - 64
#define SP7CCS3 (*(volatile int *)0x4814) // SPORT 7 multichannel compand select, channels 127 - 96

#define IISP6A (*(volatile int *)0x4840) // Internal memory DMA address
#define IMSP6A (*(volatile int *)0x4841) // Internal memory DMA access modifier
#define CSP6A (*(volatile int *)0x4842) // Contains number of DMA transfers remaining
#define CPSP6A (*(volatile int *)0x4843) // Points to next DMA parameters
#define IISP6B (*(volatile int *)0x4844) // Internal memory DMA address
#define IMSP6B (*(volatile int *)0x4845) // Internal memory DMA access modifier
#define CSP6B (*(volatile int *)0x4846) // Contains number of DMA transfers remaining
#define CPSP6B (*(volatile int *)0x4847) // Points to next DMA parameters
#define IISP7A (*(volatile int *)0x4848) // Internal memory DMA address
#define IMSP7A (*(volatile int *)0x4849) // Internal memory DMA access modifier
#define CSP7A (*(volatile int *)0x484A) // Contains number of DMA transfers remaining
#define CPSP7A (*(volatile int *)0x484B) // Points to next DMA parameters
#define IISP7B (*(volatile int *)0x484C) // Internal memory DMA address
#define IMSP7B (*(volatile int *)0x484D) // Internal memory DMA access modifier
#define CSP7B (*(volatile int *)0x484E) // Contains number of DMA transfers remaining
#define CPSP7B (*(volatile int *)0x484F) // Points to next DMA parameters
#define TXSP6A (*(volatile int *)0x4860) // SPORT 4A transmit data register
#define RXSP6A (*(volatile int *)0x4861) // SPORT 4A receive data register
#define TXSP6B (*(volatile int *)0x4862) // SPORT 4B transmit data register
#define RXSP6B (*(volatile int *)0x4863) // SPORT 4B receive data register
#define TXSP7A (*(volatile int *)0x4864) // SPORT 5A transmit data register
#define RXSP7A (*(volatile int *)0x4865) // SPORT 5A receive data register
#define TXSP7B (*(volatile int *)0x4866) // SPORT 5B transmit data register
#define RXSP7B (*(volatile int *)0x4867) // SPORT 5B receive data register

// SPI Registers
#define SPICTL (*(volatile ST_SPICTL *)0x1000) // SPI Control Register
#define SPIFLG (*(volatile ST_SPIFLG *)0x1001) // SPI Flag register
#define SPISTAT (*(volatile ST_SPISTAT *)0x1002) // SPI Status register
#define TXSPI (*(volatile int *)0x1003) // SPI transmit data register
#define RXSPI (*(volatile int *)0x1004) // SPI receive data register
#define SPIBAUD (*(volatile ST_SPIBAUD *)0x1005) // SPI baud setup register
#define RXSPI_SHADOW (*(volatile int *)0x1006) // SPI receive data shadow register
#define IISPI (*(volatile int *)0x1080) // Internal memory DMA address
#define IMSPI (*(volatile int *)0x1081) // Internal memory DMA access modifier
#define CSPI (*(volatile int *)0x1082) // Contains number of DMA transfers remaining
#define CPSPI (*(volatile int *)0x1083) // Points to next DMA parameters
#define SPIDMAC (*(volatile ST_SPIDMAC *)0x1084) // SPI DMA control register

// SPIB Registers: This SPI port is routed through the DAI
#define SPICTLB (*(volatile ST_SPICTL *)0x2800) // SPIB Control Register
#define SPIFLGB (*(volatile ST_SPIFLG *)0x2801) // SPIB Flag register
#define SPISTATB (*(volatile ST_SPISTAT *)0x2802) // SPIB Status register
#define TXSPIB (*(volatile int *)0x2803) // SPIB transmit data register
#define RXSPIB (*(volatile int *)0x2804) // SPIB receive data register
#define SPIBAUDB (*(volatile ST_SPIBAUD *)0x2805) // SPIB baud setup register
#define RXSPIB_SHADOW (*(volatile int *)0x2806) // SPIB receive data shadow register
#define IISPIB (*(volatile int *)0x2880) // Internal memory DMA address
#define IMSPIB (*(volatile int *)0x2881) // Internal memory DMA access modifier
#define CSPIB (*(volatile int *)0x2882) // Contains number of DMA transfers remaining
#define CPSPIB (*(volatile int *)0x2883) // Points to next DMA parameters
#define SPIDMACB (*(volatile ST_SPIDMAC *)0x2884) // SPIB DMA control register

// Timer Registers
#define TMSTAT (*(volatile ST_TMSTAT *)0x1400) // GP Timer Status Register
// TMxSTAT all address the same register (TMSTAT)
#define TM0STAT (*(volatile ST_TMSTAT *)0x1400) // GP Timer 0 Status register
#define TM0CTL (*(volatile ST_TMCTL *)0x1401) // GP Timer 0 Control register
#define TM0CNT (*(volatile int *)0x1402) // GP Timer 0 Count register
#define TM0PRD (*(volatile int *)0x1403) // GP Timer 0 Period register
#define TM0W (*(volatile int *)0x1404) // GP Timer 0 Width register
#define TM1STAT (*(volatile ST_TMSTAT *)0x1408) // GP Timer 1 Status register
#define TM1CTL (*(volatile ST_TMCTL *)0x1409) // GP Timer 1 Control register
#define TM1CNT (*(volatile int *)0x140a) // GP Timer 1 Count register
#define TM1PRD (*(volatile int *)0x140b) // GP Timer 1 Period register
#define TM1W (*(volatile int *)0x140c) // GP Timer 1 Width register
#define TM2STAT (*(volatile ST_TMSTAT *)0x1410) // GP Timer 2 Status register
#define TM2CTL (*(volatile ST_TMCTL *)0x1411) // GP Timer 2 Control register
#define TM2CNT (*(volatile int *)0x1412) // GP Timer 2 Count register
#define TM2PRD (*(volatile int *)0x1413) // GP Timer 2 Period register
#define TM2W (*(volatile int *)0x1414) // GP Timer 2 Width register

// POWER MGT Registers
#define PMCTL (*(volatile ST_PMCTL *)0x2000) // Power management control register
#define ROMID (*(volatile int *)0x20FF)

// DAI Registers

// DMA Parameter Registers
#define IDP_DMA_I0 (*(volatile int *)0x2400) // IDP DMA Channel 0 Index Register
#define IDP_DMA_I1 (*(volatile int *)0x2401) // IDP DMA Channel 1 Index Register
#define IDP_DMA_I2 (*(volatile int *)0x2402) // IDP DMA Channel 2 Index Register
#define IDP_DMA_I3 (*(volatile int *)0x2403) // IDP DMA Channel 3 Index Register
#define IDP_DMA_I4 (*(volatile int *)0x2404) // IDP DMA Channel 4 Index Register
#define IDP_DMA_I5 (*(volatile int *)0x2405) // IDP DMA Channel 5 Index Register
#define IDP_DMA_I6 (*(volatile int *)0x2406) // IDP DMA Channel 6 Index Register
#define IDP_DMA_I7 (*(volatile int *)0x2407) // IDP DMA Channel 7 Index Register
#define IDP_DMA_I0A (*(volatile int *)0x2408) // IDP DMA Channel 0 Index A Register for Ping Pong DMA
#define IDP_DMA_I1A (*(volatile int *)0x2409) // IDP DMA Channel 1 Index A Register for Ping Pong DMA
#define IDP_DMA_I2A (*(volatile int *)0x240a) // IDP DMA Channel 2 Index A Register for Ping Pong DMA
#define IDP_DMA_I3A (*(volatile int *)0x240b) // IDP DMA Channel 3 Index A Register for Ping Pong DMA
#define IDP_DMA_I4A (*(volatile int *)0x240c) // IDP DMA Channel 4 Index A Register for Ping Pong DMA
#define IDP_DMA_I5A (*(volatile int *)0x240d) // IDP DMA Channel 5 Index A Register for Ping Pong DMA
#define IDP_DMA_I6A (*(volatile int *)0x240e) // IDP DMA Channel 6 Index A Register for Ping Pong DMA
#define IDP_DMA_I7A (*(volatile int *)0x240f) // IDP DMA Channel 7 Index A Register for Ping Pong DMA
#define IDP_DMA_I0B (*(volatile int *)0x2418) // IDP DMA Channel 0 Index B Register for Ping Pong DMA
#define IDP_DMA_I1B (*(volatile int *)0x2419) // IDP DMA Channel 1 Index B Register for Ping Pong DMA
#define IDP_DMA_I2B (*(volatile int *)0x241a) // IDP DMA Channel 2 Index B Register for Ping Pong DMA
#define IDP_DMA_I3B (*(volatile int *)0x241b) // IDP DMA Channel 3 Index B Register for Ping Pong DMA
#define IDP_DMA_I4B (*(volatile int *)0x241c) // IDP DMA Channel 4 Index B Register for Ping Pong DMA
#define IDP_DMA_I5B (*(volatile int *)0x241d) // IDP DMA Channel 5 Index B Register for Ping Pong DMA
#define IDP_DMA_I6B (*(volatile int *)0x241e) // IDP DMA Channel 6 Index B Register for Ping Pong DMA
#define IDP_DMA_I7B (*(volatile int *)0x241f) // IDP DMA Channel 7 Index B Register for Ping Pong DMA
#define IDP_DMA_M0 (*(volatile int *)0x2410) // IDP DMA Channel 0 Modify Register
#define IDP_DMA_M1 (*(volatile int *)0x2411) // IDP DMA Channel 1 Modify Register
#define IDP_DMA_M2 (*(volatile int *)0x2412) // IDP DMA Channel 2 Modify Register
#define IDP_DMA_M3 (*(volatile int *)0x2413) // IDP DMA Channel 3 Modify Register
#define IDP_DMA_M4 (*(volatile int *)0x2414) // IDP DMA Channel 4 Modify Register
#define IDP_DMA_M5 (*(volatile int *)0x2415) // IDP DMA Channel 5 Modify Register
#define IDP_DMA_M6 (*(volatile int *)0x2416) // IDP DMA Channel 6 Modify Register
#define IDP_DMA_M7 (*(volatile int *)0x2417) // IDP DMA Channel 7 Modify Register
#define IDP_DMA_C0 (*(volatile int *)0x2420) // IDP DMA Channel 0 Count Register
#define IDP_DMA_C1 (*(volatile int *)0x2421) // IDP DMA Channel 1 Count Register
#define IDP_DMA_C2 (*(volatile int *)0x2422) // IDP DMA Channel 2 Count Register
#define IDP_DMA_C3 (*(volatile int *)0x2423) // IDP DMA Channel 3 Count Register
#define IDP_DMA_C4 (*(volatile int *)0x2424) // IDP DMA Channel 4 Count Register
#define IDP_DMA_C5 (*(volatile int *)0x2425) // IDP DMA Channel 5 Count Register
#define IDP_DMA_C6 (*(volatile int *)0x2426) // IDP DMA Channel 6 Count Register
#define IDP_DMA_C7 (*(volatile int *)0x2427) // IDP DMA Channel 7 Count Register
#define IDP_DMA_PC0 (*(volatile int *)0x2428) // IDP DMA Channel 0 Ping Pong Count Register
#define IDP_DMA_PC1 (*(volatile int *)0x2429) // IDP DMA Channel 1 Ping Pong Count Register
#define IDP_DMA_PC2 (*(volatile int *)0x242a) // IDP DMA Channel 2 Ping Pong Count Register
#define IDP_DMA_PC3 (*(volatile int *)0x242b) // IDP DMA Channel 3 Ping Pong Count Register
#define IDP_DMA_PC4 (*(volatile int *)0x242c) // IDP DMA Channel 4 Ping Pong Count Register
#define IDP_DMA_PC5 (*(volatile int *)0x242d) // IDP DMA Channel 5 Ping Pong Count Register
#define IDP_DMA_PC6 (*(volatile int *)0x242e) // IDP DMA Channel 6 Ping Pong Count Register
#define IDP_DMA_PC7 (*(volatile int *)0x242f) // IDP DMA Channel 7 Ping Pong Count Register

// SRU Registers
#define SRU_CLK0 (*(volatile ST_SRU_CLK0 *)0x2430) // SRU Clock Control Register 0
#define SRU_CLK1 (*(volatile ST_SRU_CLK1 *)0x2431) // SRU Clock Control Register 1
#define SRU_CLK2 (*(volatile ST_SRU_CLK2 *)0x2432) // SRU Clock Control Register 2
#define SRU_CLK3 (*(volatile ST_SRU_CLK3 *)0x2433) // SRU Clock Control Register 3
#define SRU_CLK4 (*(volatile ST_SRU_CLK4 *)0x2434) // SRU Clock Control Register 4
#define SRU_CLK5 (*(volatile ST_SRU_CLK5 *)0x2435) // SRU Clock Control Register 4

#define SRU_DAT0 (*(volatile ST_SRU_DAT0 *)0x2440) // SRU Data Control Register 0
#define SRU_DAT1 (*(volatile ST_SRU_DAT1 *)0x2441) // SRU Data Control Register 1
#define SRU_DAT2 (*(volatile ST_SRU_DAT2 *)0x2442) // SRU Data Control Register 2
#define SRU_DAT3 (*(volatile ST_SRU_DAT3 *)0x2443) // SRU Data Control Register 3
#define SRU_DAT4 (*(volatile ST_SRU_DAT4 *)0x2444) // SRU Data Control Register 4
#define SRU_DAT5 (*(volatile ST_SRU_DAT5 *)0x2445) // SRU Data Control Register 5
#define SRU_DAT6 (*(volatile ST_SRU_DAT6 *)0x2446) // SRU Data Control Register 5

#define SRU_FS0 (*(volatile ST_SRU_FS0 *)0x2450) // SRU FS Control Register 0
#define SRU_FS1 (*(volatile ST_SRU_FS1 *)0x2451) // SRU FS Control Register 1
#define SRU_FS2 (*(volatile ST_SRU_FS2 *)0x2452) // SRU FS Control Register 2
#define SRU_FS3 (*(volatile ST_SRU_FS3 *)0x2453) // SRU FS Control Register 3
#define SRU_FS4 (*(volatile ST_SRU_FS4 *)0x2454) // SRU FS Control Register 3

#define SRU_PIN0 (*(volatile ST_SRU_PIN0 *)0x2460) // SRU Pin Control Register 0
#define SRU_PIN1 (*(volatile ST_SRU_PIN1 *)0x2461) // SRU Pin Control Register 1
#define SRU_PIN2 (*(volatile ST_SRU_PIN2 *)0x2462) // SRU Pin Control Register 2
#define SRU_PIN3 (*(volatile ST_SRU_PIN3 *)0x2463) // SRU Pin Control Register 3
#define SRU_PIN4 (*(volatile ST_SRU_PIN4 *)0x2464) // SRU Pin Control Register 4

#define SRU_EXT_MISCA (*(volatile ST_SRU_MISCA *)0x2470) // SRU External Misc. A Control Register
#define SRU_EXT_MISCB (*(volatile ST_SRU_MISCB *)0x2471) // SRU External Misc. B Control Register

#define SRU_PBEN0 (*(volatile ST_SRU_PBEN0 *)0x2478) // SRU Pin Enable Register 0
#define SRU_PBEN1 (*(volatile ST_SRU_PBEN1 *)0x2479) // SRU Pin Enable Register 1
#define SRU_PBEN2 (*(volatile ST_SRU_PBEN2 *)0x247A) // SRU Pin Enable Register 2
#define SRU_PBEN3 (*(volatile ST_SRU_PBEN3 *)0x247B) // SRU Pin Enable Register 3

#define DAI_PIN_PULLUP (*(volatile ST_SRU_PULLUP *)0x247D) // Controls whether DAI bin buffers have pullups enabled

#define DAI_IRPTL_FE (*(volatile ST_DAI_IRPTL *)0x2480) // DAI Falling Edge Interrupt Latch Register
#define DAI_IRPTL_RE (*(volatile ST_DAI_IRPTL *)0x2481) // DAI Rising Edge Interrupt Latch Register
#define DAI_IRPTL_PRI (*(volatile ST_DAI_IRPTL *)0x2484) // DAI Interrupt Priority Register
#define DAI_IRPTL_H (*(volatile ST_DAI_IRPTL *)0x2488) // DAI High Priority Interrupt Latch Register
#define DAI_IRPTL_L (*(volatile ST_DAI_IRPTL *)0x2489) // DAI Low Priority Interrupt Latch Register
#define DAI_IRPTL_HS (*(volatile ST_DAI_IRPTL *)0x248C) // Shadow DAI High Priority Interrupt Latch Register
#define DAI_IRPTL_LS (*(volatile ST_DAI_IRPTL *)0x248D) // Shadow DAI Low Priority Interrupt Latch Register

#define IDP_CTL (*(volatile ST_IDP_CTL0 *)0x24B0) // IDP Control Register 0
#define IDP_CTL0 (*(volatile ST_IDP_CTL0 *)0x24B0) // IDP Control Register 0
#define IDP_PP_CTL (*(volatile ST_IDP_PP_CTL *)0x24B1) // IDP Parallel Port Control Register
#define IDP_CTL1 (*(volatile ST_IDP_CTL1 *)0x24B2) // IDP Control Register 1

#define DAI_STAT (*(volatile ST_DAI_STAT *)0x24B8) // DAI Status Register
#define DAI_STAT0 (*(volatile ST_DAI_STAT *)0x24B8) // DAI Status Register
#define DAI_PIN_STAT (*(volatile ST_DAI_PIN_STAT *)0x24B9) // DAI Pin Buffer Status Register
#define DAI_STAT1 (*(volatile int *)0x24BA) // DAI Status Register

#define IDP_FIFO (*(volatile ST_IDP_FIFO *)0x24D0) // IDP FIFO packing mode register

// DPI
#define SRU2_INPUT0 (*(volatile ST_SRU2_INPUT0 *)0x1C00) //SRU2_INPUT0 Register
#define SRU2_INPUT1 (*(volatile ST_SRU2_INPUT1 *)0x1C01) //SRU2_INPUT1 Register
#define SRU2_INPUT2 (*(volatile ST_SRU2_INPUT2 *)0x1C02) //SRU2_INPUT2 Register
#define SRU2_INPUT3 (*(volatile ST_SRU2_INPUT3 *)0x1C03) //SRU2_INPUT3 Register
#define SRU2_INPUT4 (*(volatile ST_SRU2_INPUT4 *)0x1C04) //SRU2_INPUT4 Register
#define SRU2_INPUT5 (*(volatile ST_SRU2_INPUT5 *)0x1C05) //SRU2_INPUT5 Register
#define SRU2_PIN0 (*(volatile ST_SRU2_PIN0 *)0x1C10) //SRU2_PIN0 Register
#define SRU2_PIN1 (*(volatile ST_SRU2_PIN1 *)0x1C11) //SRU2_PIN1 Register
#define SRU2_PIN2 (*(volatile ST_SRU2_PIN2 *)0x1C12) //SRU2_PIN2 Register
#define SRU2_PBEN0 (*(volatile ST_SRU2_PBEN0 *)0x1C20) //SRU2_PBEN0 Register
#define SRU2_PBEN1 (*(volatile ST_SRU2_PBEN1 *)0x1C21) //SRU2_PBEN1 Register
#define SRU2_PBEN2 (*(volatile ST_SRU2_PBEN2 *)0x1C22) //SRU2_PBEN2 Register

#define DPI_PIN_PULLUP (*(volatile ST_DPI_PIN_PULLUP *)0x1C30) //DPI Resistor Pull-up Enable Register
#define DPI_PIN_STAT (*(volatile ST_DPI_PIN_STAT *)0x1C31) //DPI Pin Buffer Status Register
#define DPI_IRPTL (*(volatile ST_DPI_IRPTL *)0x1C32) //DPI Interrupt Latch Register
#define DPI_IRPTL_SH (*(volatile ST_DPI_IRPTL *)0x1C33) //DPI_IRPTL Shadow Register
#define DPI_IRPTL_FE (*(volatile ST_DPI_IRPTL *)0x1C34) //Falling Edge Interrupt Mask Register
#define DPI_IRPTL_RE (*(volatile ST_DPI_IRPTL *)0x1C35) //Rising Edge Interrupt Mask Register

// PCG
#define PCG_CTLA0 (*(volatile ST_PCG_CTL0 *)0x24C0) // Precision Clock A Control Register 0
#define PCG_CTLA1 (*(volatile ST_PCG_CTL1 *)0x24C1) // Precision Clock A Control Register 1
#define PCG_CTLB0 (*(volatile ST_PCG_CTL0 *)0x24C2) // Precision Clock B Control Register 0
#define PCG_CTLB1 (*(volatile ST_PCG_CTL1 *)0x24C3) // Precision Clock B Control Register 1
#define PCG_PW (*(volatile ST_PCG_PW *)0x24C4) // Precision Clock Pulse Width Control Register
#define PCG_SYNC (*(volatile ST_PCG_SYNC *)0x24C5) // Precision Clock Frame Sync Synchronization
#define PCG_PW1 (*(volatile ST_PCG_PW *)0x24C4) // Precision Clock Pulse Width Control Register
#define PCG_SYNC1 (*(volatile ST_PCG_SYNC *)0x24C5) // Precision Clock Frame Sync Synchronization

#define PCG_CTLC0 (*(volatile ST_PCG_CTL0 *)0x24C6) // Precision Clock A Control Register 0
#define PCG_CTLC1 (*(volatile ST_PCG_CTL1 *)0x24C7) // Precision Clock A Control Register 1
#define PCG_CTLD0 (*(volatile ST_PCG_CTL0 *)0x24C8) // Precision Clock B Control Register 0
#define PCG_CTLD1 (*(volatile ST_PCG_CTL1 *)0x24C9) // Precision Clock B Control Register 1
#define PCG_PW2 (*(volatile ST_PCG_PW *)0x24CA) // Precision Clock Pulse Width Control Register
#define PCG_SYNC2 (*(volatile ST_PCG_SYNC2 *)0x24CB) // Precision Clock Frame Sync Synchronization

// Peripheral Interrupt priority control register
#define PICR0 (*(volatile ST_PICR0 *)0x2200) //Peripheral Interrupt Priority0 Control Register
#define PICR1 (*(volatile ST_PICR1 *)0x2201) //Peripheral Interrupt Priority1 Control Register
#define PICR2 (*(volatile ST_PICR2 *)0x2202) //Peripheral Interrupt Priority2 Control Register
#define PICR3 (*(volatile ST_PICR3 *)0x2203) //Peripheral Interrupt Priority3 Control Register

// MTM registers
#define MTMCTL (*(volatile ST_MTMCTL *)0x2c01) //Memory-to-Memory DMA Control Register
#define IIMTMW (*(volatile int *)0x2c10) //MTM DMA Destination Index Register
#define IIMTMR (*(volatile int *)0x2c11) //MTM DMA Source Index Register
#define IMMTMW (*(volatile int *)0x2c0e) //MTM DMA Destination Modify Register
#define IMMTMR (*(volatile int *)0x2c0f) //MTM DMA Source Modify Register
#define CMTMW (*(volatile int *)0x2c16) //MTM DMA Destination Count Register
#define CMTMR (*(volatile int *)0x2c17) //MTM DMA Source Count Register

// PWM
#define PWMGCTL (*(volatile ST_PWMGCTL *)0x3800) // PWM Global Control Register
#define PWMGSTAT (*(volatile ST_PWMGSTAT *)0x3801) // PWM Global Status Register

#define PWMCTL0 (*(volatile ST_PWMCTL *)0x3000) // PWM Control
#define PWMSTAT0 (*(volatile ST_PWMSTAT *)0x3001) // PWM Status
#define PWMPERIOD0 (*(volatile int *)0x3002) // PWM Period Register
#define PWMDT0 (*(volatile int *)0x3003) // PWM Dead Time Register
#define PWMA0 (*(volatile int *)0x3005) // PWM Channel A Duty Control
#define PWMB0 (*(volatile int *)0x3006) // PWM Channel B Duty Control
#define PWMSEG0 (*(volatile ST_PWMSEG *)0x3008) // PWM Output Enable
#define PWMAL0 (*(volatile int *)0x300A) // PWM Channel AL Duty Control
#define PWMBL0 (*(volatile int *)0x300B) // PWM Channel BL Duty Control
#define PWMDBG0 (*(volatile int *)0x300E) // PWM Debug Status
#define PWMPOL0 (*(volatile ST_PWMPOL *)0x300F) // PWM Output polarity select

#define PWMCTL1 (*(volatile ST_PWMCTL *)0x3010) // PWM Control
#define PWMSTAT1 (*(volatile ST_PWMSTAT *)0x3011) // PWM Status
#define PWMPERIOD1 (*(volatile int *)0x3012) // PWM Period Register
#define PWMDT1 (*(volatile int *)0x3013) // PWM Dead Time Register
#define PWMA1 (*(volatile int *)0x3015) // PWM Channel A Duty Control
#define PWMB1 (*(volatile int *)0x3016) // PWM Channel B Duty Control
#define PWMSEG1 (*(volatile ST_PWMSEG *)0x3018) // PWM Output Enable
#define PWMAL1 (*(volatile int *)0x301A) // PWM Channel AL Duty Control
#define PWMBL1 (*(volatile int *)0x301B) // PWM Channel BL Duty Control
#define PWMDBG1 (*(volatile int *)0x301E) // PWM Debug Status
#define PWMPOL1 (*(volatile ST_PWMPOL *)0x301F) // PWM Output polarity select

#define PWMCTL2 (*(volatile ST_PWMCTL *)0x3400) // PWM Control
#define PWMSTAT2 (*(volatile ST_PWMSTAT *)0x3401) // PWM Status
#define PWMPERIOD2 (*(volatile int *)0x3402) // PWM Period Register
#define PWMDT2 (*(volatile int *)0x3403) // PWM Dead Time Register
#define PWMA2 (*(volatile int *)0x3405) // PWM Channel A Duty Control
#define PWMB2 (*(volatile int *)0x3406) // PWM Channel B Duty Control
#define PWMSEG2 (*(volatile ST_PWMSEG *)0x3408) // PWM Output Enable
#define PWMAL2 (*(volatile int *)0x340A) // PWM Channel AL Duty Control
#define PWMBL2 (*(volatile int *)0x340B) // PWM Channel BL Duty Control
#define PWMDBG2 (*(volatile int *)0x340E) // PWM Debug Status
#define PWMPOL2 (*(volatile ST_PWMPOL *)0x340F) // PWM Output polarity select

#define PWMCTL3 (*(volatile ST_PWMCTL *)0x3410) // PWM Control
#define PWMSTAT3 (*(volatile ST_PWMSTAT *)0x3411) // PWM Status
#define PWMPERIOD3 (*(volatile int *)0x3412) // PWM Period Register
#define PWMDT3 (*(volatile int *)0x3413) // PWM Dead Time Register
#define PWMA3 (*(volatile int *)0x3415) // PWM Channel A Duty Control
#define PWMB3 (*(volatile int *)0x3416) // PWM Channel B Duty Control
#define PWMSEG3 (*(volatile ST_PWMSEG *)0x3418) // PWM Output Enable
#define PWMAL3 (*(volatile int *)0x341A) // PWM Channel AL Duty Control
#define PWMBL3 (*(volatile int *)0x341B) // PWM Channel BL Duty Control
#define PWMDBG3 (*(volatile int *)0x341E) // PWM Debug Status
#define PWMPOL3 (*(volatile ST_PWMPOL *)0x341F) // PWM Output polarity select

// Registers for UART0
#define UART0THR (*(volatile ST_UARTTHR *)0x3c00) // Transmit Holding Register
#define UART0RBR (*(volatile ST_UARTRBR *)0x3c00) // Receive Buffer Register
#define UART0DLL (*(volatile int *)0x3c00) // Divisor Latch Low Byte
#define UART0IER (*(volatile ST_UARTIER *)0x3c01) // Interrupt Enable Register
#define UART0DLH (*(volatile int *)0x3c01) // Divisor Latch High Byte
#define UART0IIR (*(volatile ST_UARTIIR *)0x3c02) // Interrupt Identification Register
#define UART0LCR (*(volatile ST_UARTLCR *)0x3c03) // Line Control Register
#define UART0MODE (*(volatile ST_UARTMODE *)0x3c04) // Mode Register
#define UART0LSR (*(volatile ST_UARTLSR *)0x3c05) // Line Status Register
#define UART0SCR (*(volatile int *)0x3c07) // Scratch Register
#define UART0RBRSH (*(volatile ST_UARTRBR *)0x3c08) // Read Buffer Shadow Register
#define UART0IIRSH (*(volatile ST_UARTIIR *)0x3c09) // Interrupt Identification Shadow Register
#define UART0LSRSH (*(volatile ST_UARTLSR *)0x3c0a) // Line Status Shadow Register

#define IIUART0RX (*(volatile int *)0x3e00) // Internal Memory address for DMA access with UART Receiver
#define IMUART0RX (*(volatile int *)0x3e01) // Internal Memory modifier for DMA access with UART Receiver
#define CUART0RX (*(volatile int *)0x3e02) // Word Count for DMA access with UART Receiver
#define CPUART0RX (*(volatile int *)0x3e03) // Chain Point for DMA access with UART Receiver
#define UART0RXCTL (*(volatile ST_UARTCTL *)0x3e04) // UART Receiver control register
#define UART0RXSTAT (*(volatile ST_UARTRXSTAT *)0x3e05) // UART Receiver status register

#define IIUART0TX (*(volatile int *)0x3f00) // Internal Memory address for DMA access with UART Transmitter
#define IMUART0TX (*(volatile int *)0x3f01) // Internal Memory modifier for DMA access with UART Transmitter
#define CUART0TX (*(volatile int *)0x3f02) // Word Count for DMA access with UART Transmitter
#define CPUART0TX (*(volatile int *)0x3f03) // Chain Point for DMA access with UART Transmitter
#define UART0TXCTL (*(volatile ST_UARTCTL *)0x3f04) // UART Transmitter control register
#define UART0TXSTAT (*(volatile ST_UARTTXSTAT *)0x3f05) // UART Transmitter status register

/* Register definition for UART1 */
#define UART1THR (*(volatile ST_UARTTHR *)0x4000) // Transmit Holding Register
#define UART1RBR (*(volatile ST_UARTRBR *)0x4000) // Receive Buffer Register
#define UART1DLL (*(volatile int *)0x4000) // Divisor Latch Low Byte
#define UART1IER (*(volatile ST_UARTIER *)0x4001) // Interrupt Enable Register
#define UART1DLH (*(volatile int *)0x4001) // Divisor Latch High Byte
#define UART1IIR (*(volatile ST_UARTIIR *)0x4002) // Interrupt Identification Register
#define UART1LCR (*(volatile ST_UARTLCR *)0x4003) // Line Control Register
#define UART1MODE (*(volatile ST_UARTMODE *)0x4004) // Mode Register
#define UART1LSR (*(volatile ST_UARTLSR *)0x4005) // Line Status Register
#define UART1SCR (*(volatile int *)0x4007) // Scratch Register
#define UART1RBRSH (*(volatile ST_UARTRBR *)0x4008) // Read Buffer Shadow Register
#define UART1IIRSH (*(volatile ST_UARTIIR *)0x4009) // Interrupt Identification Shadow Register
#define UART1LSRSH (*(volatile ST_UARTLSR *)0x400a) // Line Status Shadow Register

#define IIUART1RX (*(volatile int *)0x4200) // Internal Memory address for DMA access with Receiver
#define IMUART1RX (*(volatile int *)0x4201) // Internal Memory modifier for DMA access with Receiver
#define CUART1RX (*(volatile int *)0x4202) // Word Count for DMA access with Receiver
#define CPUART1RX (*(volatile int *)0x4203) // Chain Point for DMA access with Receiver
#define UART1RXCTL (*(volatile ST_UARTCTL *)0x4204) // Receiver control register
#define UART1RXSTAT (*(volatile ST_UARTRXSTAT *)0x4205) // Receiver status register

#define IIUART1TX (*(volatile int *)0x4300) // Internal Memory address for DMA access with Transmitter
#define IMUART1TX (*(volatile int *)0x4301) // Internal Memory modifier for DMA access with Transmitter
#define CUART1TX (*(volatile int *)0x4302) // Word Count for DMA access with Transmitter
#define CPUART1TX (*(volatile int *)0x4303) // Chain Point for DMA access with Transmitter
#define UART1TXCTL (*(volatile ST_UARTCTL *)0x4304) // Transmitter control register
#define UART1TXSTAT (*(volatile ST_UARTTXSTAT *)0x4305) // Transmitter status register

// Registers Poiter for UART0
#define pUART0THR ((volatile ST_UARTTHR *)0x3c00) // Transmit Holding Register
#define pUART0RBR ((volatile ST_UARTRBR *)0x3c00) // Receive Buffer Register
#define pUART0DLL ((volatile int *)0x3c00) // Divisor Latch Low Byte
#define pUART0IER ((volatile ST_UARTIER *)0x3c01) // Interrupt Enable Register
#define pUART0DLH ((volatile int *)0x3c01) // Divisor Latch High Byte
#define pUART0IIR ((volatile ST_UARTIIR *)0x3c02) // Interrupt Identification Register
#define pUART0LCR ((volatile ST_UARTLCR *)0x3c03) // Line Control Register
#define pUART0MODE ((volatile ST_UARTMODE *)0x3c04) // Mode Register
#define pUART0LSR ((volatile ST_UARTLSR *)0x3c05) // Line Status Register
#define pUART0SCR ((volatile int *)0x3c07) // Scratch Register
#define pUART0RBRSH ((volatile ST_UARTRBR *)0x3c08) // Read Buffer Shadow Register
#define pUART0IIRSH ((volatile ST_UARTIIR *)0x3c09) // Interrupt Identification Shadow Register
#define pUART0LSRSH ((volatile ST_UARTLSR *)0x3c0a) // Line Status Shadow Register

#define pIIUART0RX ((volatile int *)0x3e00) // Internal Memory address for DMA access with UART Receiver
#define pIMUART0RX ((volatile int *)0x3e01) // Internal Memory modifier for DMA access with UART Receiver
#define pCUART0RX ((volatile int *)0x3e02) // Word Count for DMA access with UART Receiver
#define pCPUART0RX ((volatile int *)0x3e03) // Chain Point for DMA access with UART Receiver
#define pUART0RXCTL ((volatile ST_UARTCTL *)0x3e04) // UART Receiver control register
#define pUART0RXSTAT ((volatile ST_UARTRXSTAT *)0x3e05) // UART Receiver status register

#define pIIUART0TX ((volatile int *)0x3f00) // Internal Memory address for DMA access with UART Transmitter
#define pIMUART0TX ((volatile int *)0x3f01) // Internal Memory modifier for DMA access with UART Transmitter
#define pCUART0TX ((volatile int *)0x3f02) // Word Count for DMA access with UART Transmitter
#define pCPUART0TX ((volatile int *)0x3f03) // Chain Point for DMA access with UART Transmitter
#define pUART0TXCTL ((volatile ST_UARTCTL *)0x3f04) // UART Transmitter control register
#define pUART0TXSTAT ((volatile ST_UARTTXSTAT *)0x3f05) // UART Transmitter status register

/* Register Poiter for UART1 */
#define pUART1THR ((volatile ST_UARTTHR *)0x4000) // Transmit Holding Register
#define pUART1RBR ((volatile ST_UARTRBR *)0x4000) // Receive Buffer Register
#define pUART1DLL ((volatile int *)0x4000) // Divisor Latch Low Byte
#define pUART1IER ((volatile ST_UARTIER *)0x4001) // Interrupt Enable Register
#define pUART1DLH ((volatile int *)0x4001) // Divisor Latch High Byte
#define pUART1IIR ((volatile ST_UARTIIR *)0x4002) // Interrupt Identification Register
#define pUART1LCR ((volatile ST_UARTLCR *)0x4003) // Line Control Register
#define pUART1MODE ((volatile ST_UARTMODE *)0x4004) // Mode Register
#define pUART1LSR ((volatile ST_UARTLSR *)0x4005) // Line Status Register
#define pUART1SCR ((volatile int *)0x4007) // Scratch Register
#define pUART1RBRSH ((volatile ST_UARTRBR *)0x4008) // Read Buffer Shadow Register
#define pUART1IIRSH ((volatile ST_UARTIIR *)0x4009) // Interrupt Identification Shadow Register
#define pUART1LSRSH ((volatile ST_UARTLSR *)0x400a) // Line Status Shadow Register

#define pIIUART1RX ((volatile int *)0x4200) // Internal Memory address for DMA access with Receiver
#define pIMUART1RX ((volatile int *)0x4201) // Internal Memory modifier for DMA access with Receiver
#define pCUART1RX ((volatile int *)0x4202) // Word Count for DMA access with Receiver
#define pCPUART1RX ((volatile int *)0x4203) // Chain Point for DMA access with Receiver
#define pUART1RXCTL ((volatile ST_UARTCTL *)0x4204) // Receiver control register
#define pUART1RXSTAT ((volatile ST_UARTRXSTAT *)0x4205) // Receiver status register

#define pIIUART1TX ((volatile int *)0x4300) // Internal Memory address for DMA access with Transmitter
#define pIMUART1TX ((volatile int *)0x4301) // Internal Memory modifier for DMA access with Transmitter
#define pCUART1TX ((volatile int *)0x4302) // Word Count for DMA access with Transmitter
#define pCPUART1TX ((volatile int *)0x4303) // Chain Point for DMA access with Transmitter
#define pUART1TXCTL ((volatile ST_UARTCTL *)0x4304) // Transmitter control register
#define pUART1TXSTAT ((volatile ST_UARTTXSTAT *)0x4305) // Transmitter status register

/* TWI Registers */
#define TWIDIV (*(volatile ST_TWIDIV *)0x4400) // TWI Serial Clock Divider
#define TWIMITR (*(volatile int *)0x4404) // TWI Master Internal Time Reference
#define TWISCTL (*(volatile ST_TWISCTL *)0x4408) // TWI Slave Mode Control Register
#define TWISSTAT (*(volatile ST_TWISSTAT *)0x440C) // TWI Slave Mode Status Register
#define TWISADDR (*(volatile int *)0x4410) // TWI Slave Mode Address Comparison Register
#define TWIMCTL (*(volatile ST_TWIMCTL *)0x4414) // TWI Master Mode Control Register
#define TWIMSTAT (*(volatile ST_TWIMSTAT *)0x4418) // TWI Master Mode Status Register
#define TWIMADDR (*(volatile int *)0x441C) // TWI Master Mode Address Register
#define TWIIRPTL (*(volatile ST_TWIIRPTL *)0x4420) // TWI Interrupt Latch Register
#define TWIIMASK (*(volatile ST_TWIIMASK *)0x4424) // TWI Interrupt Mask Register
#define TWIFIFOCTL (*(volatile ST_TWIFIFOCTL *)0x4428) // TWI FIFO Control Register
#define TWIFIFOSTAT (*(volatile ST_TWIFIFOSTAT *)0x442C) // TWI FIFO Status Register
#define TXTWI8 (*(volatile int *)0x4480) // TWI 8-Bit Transmit FIFO Register
#define TXTWI16 (*(volatile ST_TWI16 *)0x4484) // TWI 16-Bit Transmit FIFO Register
#define RXTWI8 (*(volatile int *)0x4488) // TWI 8-Bit Receive FIFO Register
#define RXTWI16 (*(volatile ST_TWI16 *)0x448C) // TWI 16-Bit Receive FIFO Register

// Sample Rate Converter registers
#define SRCCTL0 (*(volatile ST_SRCCTL0 *)0x2490) // SRC0 Control register
#define SRCCTL1 (*(volatile ST_SRCCTL1 *)0x2491) // SRC1 Control register
#define SRCMUTE (*(volatile ST_SRCMUTE *)0x2492) // SRC Mute register
#define SRCRAT0 (*(volatile ST_SRCRAT0 *)0x2498) // SRC0 Output to Input Ratio
#define SRCRAT1 (*(volatile ST_SRCRAT1 *)0x2499) // SRC1 Output to Input Ratio

// SPDIF Transmit registers
#define DITCTL (*(volatile ST_DITCTL *)0x24A0) // Digital Interface Transmit Control Register

// Channel Status buffer
#define DITCHANA0 (*(volatile ST_DITCHAN0 *)0x24A1) //Left Channel Status for Subframe A Register 0
#define DITCHANA1 (*(volatile ST_DITCHAN1 *)0x24D4) //Left Channel Status for Subframe A Register 1
#define DITCHANA2 (*(volatile ST_DITCHAN2 *)0x24D5) //Left Channel Status for Subframe A Register 2
#define DITCHANA3 (*(volatile ST_DITCHAN3 *)0x24D6) //Left Channel Status for Subframe A Register 3
#define DITCHANA4 (*(volatile ST_DITCHAN4 *)0x24D7) //Left Channel Status for Subframe A Register 4
#define DITCHANA5 (*(volatile ST_DITCHAN5 *)0x24D8) //Left Channel Status for Subframe A Register 5
#define DITCHANB0 (*(volatile ST_DITCHAN0 *)0x24A2) //Right Channel Status for Subframe B Register 0
#define DITCHANB1 (*(volatile ST_DITCHAN1 *)0x24DA) //Right Channel Status for Subframe B Register 1
#define DITCHANB2 (*(volatile ST_DITCHAN2 *)0x24DB) //Right Channel Status for Subframe B Register 2
#define DITCHANB3 (*(volatile ST_DITCHAN3 *)0x24DC) //Right Channel Status for Subframe B Register 3
#define DITCHANB4 (*(volatile ST_DITCHAN4 *)0x24DD) //Right Channel Status for Subframe B Register 4
#define DITCHANB5 (*(volatile ST_DITCHAN5 *)0x24DE) //Right Channel Status for Subframe B Register 5

// User bit buffers
#define DITUSRBITA0 (*(volatile ST_DITUSRBIT0 *)0x24E0) //User Bits Buffer Registers for Subframe A Register 0
#define DITUSRBITA1 (*(volatile ST_DITUSRBIT1 *)0x24E1) //User Bits Buffer Registers for Subframe A Register 1
#define DITUSRBITA2 (*(volatile ST_DITUSRBIT2 *)0x24E2) //User Bits Buffer Registers for Subframe A Register 2
#define DITUSRBITA3 (*(volatile ST_DITUSRBIT3 *)0x24E3) //User Bits Buffer Registers for Subframe A Register 3
#define DITUSRBITA4 (*(volatile ST_DITUSRBIT4 *)0x24E4) //User Bits Buffer Registers for Subframe A Register 4
#define DITUSRBITA5 (*(volatile ST_DITUSRBIT5 *)0x24E5) //User Bits Buffer Registers for Subframe A Register 5

#define DITUSRBITB0 (*(volatile ST_DITUSRBIT0 *)0x24E8) //User Bits Buffer Registers for Subframe B Register 0
#define DITUSRBITB1 (*(volatile ST_DITUSRBIT1 *)0x24E9) //User Bits Buffer Registers for Subframe B Register 1
#define DITUSRBITB2 (*(volatile ST_DITUSRBIT2 *)0x24EA) //User Bits Buffer Registers for Subframe B Register 2
#define DITUSRBITB3 (*(volatile ST_DITUSRBIT3 *)0x24EB) //User Bits Buffer Registers for Subframe B Register 3
#define DITUSRBITB4 (*(volatile ST_DITUSRBIT4 *)0x24EC) //User Bits Buffer Registers for Subframe B Register 4
#define DITUSRBITB5 (*(volatile ST_DITUSRBIT5 *)0x24ED) //User Bits Buffer Registers for Subframe B Register 5

// SPDIF Receiver registers
#define DIRCTL (*(volatile ST_DIRCTL *)0x24A8) // Digital Interface Receiver Control Register
#define DIRSTAT (*(volatile ST_DIRSTAT *)0x24A9) // Digital Interface Receiver Status
#define DIRCHANL (*(volatile ST_DIRCHANL *)0x24AA) // Digital Interface Receiver Left Channel Status
#define DIRCHANR (*(volatile ST_DIRCHANR *)0x24AB) // Digital Interface Receiver Right Channel Status

#endif  //__ES_ADSP21369REG_H_