1 Introduction
In the past, SRAM is widely used for small volume runtime data storage. With the increase of RAM demand and speed, SRAM is not appropriate. Synchronous DRAM (SDRAM) has become the choice of medium volume and speed, with less timing hassle than DRAM. This section demonstrates an example of 16-bit SDRAM interfacing with ADSP-21369 and its programming.
2 Hardware Interface
In some applications, part of the ADSP-21369 data bus is used for other purposes than data bus. For example, since PWM pins are multiplexed with DB[31:16], when PWM module is needed, only DB[15:0] are available for data bus. Thus, we can use only 16 data bit peripherals. A typical hardware interface of the DSP with Micron MT48LC4M16A2 is shown in Figure 1. Note that A11-A0 from DSP is connected to A11-A0 of the 16-bit SDRAM, while A0 is not used in 32-bit SDRAM interface, i.e., A13-A1 is connected to A12-A0 of 32-bit SDRAM.
Figure 1 - 16-bit SDRAM MT48LC4M16 Hardware Interface Example
3 Address Range
Since the DSP is 32-bit, while the SDRAM is 16 bit, the DSP accesses two consecutive locations in read and write to make 32-bit word. Therefore, the address range in 32-bit is half of the SDRAM in 16-bit. For example, interfacing with Micron MT48LC4M16A2, which is a 4 M x 16 chip, whose address range is 0x0 – 0x400000 in 16-bit, but from the DSP perspective, accessible address range is 0x0 – 0x200000 in 32-bit.
4 Initialization
The initialization for SDRAM includes the enabling of SDRAM controller module by the initialization of Power Management Control register (PMCTL), the setting of chip select signal, the initialization of SDRAM control register (SDCTL) and refresh rate control register (SDRRC). It is the SDCTL register that enables or disables the SDRAM signals.
4.1 PMCTL Initialization
Two bits in PMCTL register are related to SDRAM, the module enable bit and SDCLK. Setting SDRAMOFF bit to 0 enables SDRAM module. SDCLK is determined by setting the core clock to SD clock ratio. For example, core clock is 320 MHz, and you want SDRAM runs at 128 MHz, set the ratio to 2.5, i.e., 320 MHz / 2.5 = 128 MHz.
//PMCTL register sets the SDCLK frequency and enables the SDRAM controller
PMCTL.SDRAMOFF = 0; //enables SDRAM module
PMCTL.SDCKR = 1; //sets CCLK_SDCLK_RATIO 2.5
4.2 EPCTL Initialization
There are four Chip Select signals, MS3-MS0, which can be used to select SDRAM. If either MS0 or MS1 is used for SDRAM Chip Select (SDCS), just set the respective bit in EPCTL to 1.
EPCTL.B0SD = 1; //if MS0 is used as SDCS
EPCTL.B1SD = 1; //if MS1 is used as SDCS
However, if MS2 or MS3 is used for SDCS, the MSEN bit in the System Control register (SYSCTL) must be set to 1 in addition to the setting of the bit in EPCTL, because MS2 and MS3 are multiplexed with Flag2 and Flag3. The code is shown as below.
SYSCTL.MSEN = 1;
EPCTL.B2SD = 1; //if MS2 is used as SDCS
EPCTL.B3SD = 1; //if MS3 is used as SDCS
4.3 SDRRC Initialization
To generate a proper background auto-refresh cycles, a correct refresh rate count value shall be set to SDRRC register. The value is calculated based on SDCLK and the parameters of the SDRAM. Use the following equation.
RDIV = (fSDCLK x tREF / NRA) – (tRAS + tRP)
Where
fSDCLK – SDRAM clock frequency (SDCLK)
tREF – SDRAM refresh period
NRA – Number of Row Address in SDRAM
tRAS – Active to precharge time in the number of clock cycles
tRP – RAS to precharge time in the number of clock cycles
e.g., fSDCLK = 128 MHz, tREF = 64 ms, NRA = 4096 (12 bit row address width), tRAS = 6, tRP = 3, then
RDIV = (128^6 x 64^-3 / 4096) – (6 + 3) = 1991
Set the value to SDRRC.
SDRRC.RDIV = 1991; //refresh divisor
4.4 SDCTL Initialization
SDCTL register enables signal outputs and configures all timing parameters, such as tRAS, tRP, tWR, and tRCD. Check the time requirements of the SDRAM, use the equation below to determine the value of each timing parameter.
Value = Time (ns) / SDCLK Period (ns)
For example, for MT48LC4M16A2-75, tRAS = 44 ns, SDCLK period = 7.8 ns,
SDTRAS = 44 ns / 7.8 ns = 6 cycles (the greater integer)
Whether self refresh or auto refresh mode shall be chosen depends on the SDRAM type. If the SDRAM is a physical device, self refresh mode can be chosen, in which mode refresh occurs inside the SDRAM chip which reduces the power consumption. However, if the SDRAM is built in FPGA, the auto refresh mode shall be used, in which mode the refresh signals (SDCS, SDCAS, SDRAS) from the DSP occur every time when the refresh counter expires.
After setting the register, a dummy read or write to memory must be executed to trigger the power up sequence. At the completion of the power up sequence, the SDCI bit of SDRAM Status register (SDSTAT) changes from 0 to 1.
//SDCTL configuration
ST_SDCTL sdctl;
sdctl.ALL = 0;
sdctl.BIT.DSDCTL = 0; //enable SDRAM clock and signals
sdctl.BIT.DSDCLK1 = 1; //disable SDRAM clock 1
sdctl.BIT.SDCL = 3; //SDRAM CAS Latency = 3 cycles
sdctl.BIT.SDTRAS = 6; //SDRAM tRAS Spec = 44 / 7.8 = 6 cycles
sdctl.BIT.SDTRP = 3; //SDRAM tRP Spec = 20 / 7.8 = 3
sdctl.BIT.SDTWR = 2; //SDRAM tWR Spec = (7.8 + 7.5) / 7.8 = 2 cycles
sdctl.BIT.SDTRCD = 3; //SDRAM tRCD Spec = 20 / 7.8 = 3 cycles
sdctl.BIT.SDCAW = 0; //SDRAM Bank Column Address Width = 8 bits
sdctl.BIT.SDRAW = 4; //SDRAM Row Address Width = 12 bits
sdctl.BIT.X16DE = 1; //16 bit data bus width
sdctl.BIT.SDBUF = 0; //no buffer option
sdctl.BIT.PH_SDSRF = 1; //enable self refresh
sdctl.BIT.PH_SDORF = 1; //disable auto refresh
sdctl.BIT.SDPM = 0; //Power up mode
sdctl.BIT.SDPSS = 1; //Start SDRAM Power up Sequence
SDCTL.ALL = sdctl.ALL;
//dummy read to trigger power-up sequence
INT32 temp = *(INT32 *)0x200000;
5 Wave Form
As ADSP-21369 is 32-bit DSP, while MT48LC4M16 is a 16-bit SDRAM, the DSP access twice as it writes to or reads data from the SDRAM. A write wave form example is shown in Figure 2, and a read wave form example is shown in Figure 3. 
Figure 2 - ADSP-21369 writes data to the 16-bit SDRAM 
Figure 3 - ADSP-21369 reads data from the 16-bit SDRAM 5 Source Code for Download
A sample code for SDRAM configuration and test can be downloaded here.
ES_SDRAM_Init.c
ES_SDRAM_Test.c
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