/*  This program configures the processor for proper operation		*/
/*									*/

.file_attr libGroup="crt";
.file_attr libName="libc";
.file_attr libFunc="___lib_setup_processor";
.file_attr FuncName="___lib_setup_processor";
.file_attr libFunc="___lib_setup_hardware";
.file_attr FuncName="___lib_setup_hardware";
.file_attr prefersMem="any";
.file_attr prefersMemNum="50";

.file_attr libFunc="___lib_setup_c";

#include "lib_glob.h"

.SEGMENT/CODE	    Code_Space_Name;
.FILE RTL_FILENAME;

.EXTERN	    ___inits;
.GLOBAL	    ___lib_setup_processor;
.GLOBAL	    ___lib_setup_hardware;

#ifdef _ADI_SWFA
.EXTERN     __21160_anomaly_write_location;
#endif

___lib_setup_processor:	CALL (PC, ___lib_setup_registers);
			CALL (PC, ___lib_setup_modes);
			JUMP (PC, ___lib_setup_memory);	/* RTS eliminated */

___lib_clear_irptl:	
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
      LIRPTL = 0 ;
      IMASKP = 0 ;
#endif
      RTS (DB);
			IRPTL = 0;	/* Clear interrupt latch for hardware*/
			nop;

#if !defined(__ADSP21020__)
/* IMPORTANT NOTE: The cache MUST be cleared before ANY PMDA accesses are made! */
___lib_clear_cache:	BIT SET MODE2 0x10; /* Clear cache for rev 0 hardware*/
                        	                /* MODE2 is a latent write */
#ifdef __213xx__
          // The cache isn't enabled properly on some 2136x chips, so do this.
          nop;     // MODE1 latency
          READ CACHE 0;
#endif
          RTS (DB);
          FLUSH CACHE;
          BIT CLR MODE2 0x10;
#endif

___lib_setup_registers:	LCNTR=2, do (PC, end_setup) until LCE;
			 NOP;   /* TAR-1904: one-cycle delay requires NOP so alternate M15
					can be properly initialized. */
			 M15=-1;
			 M7=-1;
			 M14=1;
			 M6=1;
			 M13=0;
			 M5=0;
			 L0=0;
			 L1=0;
			 L2=0;
			 L3=0;
			 L4=0;
			 L5=0;
			 L6=0;
			 L7=0;
			 L8=0;
			 L9=0;
			 L10=0;
			 L11=0;
			 L12=0;
			 L13=0;
			 L14=0;
			 L15=0;
			 B0=0;
			 B1=0;
			 B2=0;
			 B3=0;
			 B4=0;
			 B5=0;
			 B6=0;
			 B7=0;
			 B8=0;
			 B9=0;
			 B10=0;
			 B11=0;
			 B12=0;
			 B13=0;
			 B14=0;
			 B15=0;
end_setup: BIT SET MODE1 0x78;	/* setup secondary dags too*/

			BIT CLR MODE1 0x78;	/* reset to primary dags*/
			RTS;

___lib_setup_modes:
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
			BIT SET MODE1 0x1011800;	/*Set to 32-bit mode and enable CBUFEN */
			MMASK = 0xE03003;		/* We want to disable IRPTEN, saturation, SIMD, broadcast loads, bit reversal. */

#else
			BIT SET MODE1 0x11800;	/*Set to 32-bit mode*/
#endif
			RTS;			/*Set global interrupt enable*/
						/*Set interrupt nesting enable*/

___lib_setup_memory:	PX=PM(___inits);	/*Read address of table*/
			R0=PX2;			/*B'cse seg_init is 48 bits*/
			R0=PASS R0, I8=R0;	/*Test no inits, pts to init_seg*/
			IF EQ RTS ; 		/*Return now from no inits*/
			
zero_dm:		PX=PM(I8,M14);		/*Read number of DM zero inits*/
			R0=PX2;			/*B'cse seg_init is 48 bits*/
			R0=PASS R0;		/*Test for no DM zero inits*/
			IF EQ JUMP (PC, zero_pm); /*No DM zero inits*/
			LCNTR=R0, DO zero_inits_dm UNTIL LCE;
				PX=PM(I8,M14);	/*Read zero init block*/
				I0=PX2;		/*Load pointer to block begin*/
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
                R0 = PX1;  /**/
                R0 = FEXT R0 BY 16:16;
				LCNTR=R0, DO zero_blk_dm UNTIL LCE;
#else
				LCNTR=PX1, DO zero_blk_dm UNTIL LCE;
#endif
zero_blk_dm:				DM(I0,M6)=0;
zero_inits_dm:			NOP;		/*Dead instruction*/

zero_pm:		PX=PM(I8,M14);		/*Read number of PM zero inits*/
			R0=PX2;
			R0=PASS R0;             /*Test for no PM zero inits*/ 
                        IF EQ JUMP (PC, init_dm); /*No PM zero inits*/
                        LCNTR=R0, DO zero_inits_pm UNTIL LCE; 
                                PX=PM(I8,M14);  /*Read zero init block*/ 
                                I9=PX2;         /*Load pointer to block begin*/ 
				R0=PX1;
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
                R0 = FEXT R0 BY 16:16;
#endif
				PX=0;
                                LCNTR=R0, DO zero_blk_pm UNTIL LCE; 
#if defined(__2126x__) && defined(__WORKAROUND_2126X_ANOMALY4__)
zero_blk_pm:                         PM(I9,M14)=PX; nop; /* 48 bits init */
#else
zero_blk_pm:                         PM(I9,M14)=PX; /* 48 bits init */
#endif
#ifdef _ADI_SWFA
                                     PM(__21160_anomaly_write_location)=r0;
                                     PM(__21160_anomaly_write_location)=r0;
#endif
zero_inits_pm:			NOP;            /*Dead instruction*/ 
init_dm:		PX=PM(I8,M14);		/*Read number of DM blk inits*/
			R0=PX2;
			R0=PASS R0;		/*Check for no DM blk inits*/
			IF EQ JUMP (PC, init_pm); /*Do PM inits*/
			LCNTR=R0, DO blk_inits_dm UNTIL LCE;
				PX=PM(I8,M14);	/*Read address and count */
                         	I0=PX2;		/*Set beginning address*/
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
                R0 = PX1;  /**/
                R0 = FEXT R0 BY 16:16;
				LCNTR=R0, DO init_blk_dm UNTIL LCE;
#else
				LCNTR=PX1, DO init_blk_dm UNTIL LCE;
#endif
					PX=PM(I8,M14);
					R0=PX2;
init_blk_dm:				DM(I0,M6)=R0;
blk_inits_dm:			NOP;		/*Dead instruction*/

init_pm:		PX=PM(I8,M14);		/*Read number of PM blk inits*/
			R0=PX2;
			R0=PASS R0;		/*Check for no PM blk inits*/
			IF EQ JUMP (PC, finish_inits); /*Jump to clean up*/
			LCNTR=R0, DO blk_inits_pm UNTIL LCE;
				PX=PM(I8,M14);	/*Read address and count*/
				I9=PX2;		/*Point to blk begin*/
#if defined(__2116x__) || defined(__2126x__) || defined(__213xx__)
                R0 = PX1;  /**/
                R0 = FEXT R0 BY 16:16;
				LCNTR=R0, DO init_blk_pm UNTIL LCE;
#else
				LCNTR=PX1, DO init_blk_pm UNTIL LCE;
#endif
					PX=PM(I8,M14);
#ifdef _ADI_SWFA
					PM(I9,M14)=PX;
					pm(__21160_anomaly_write_location)=r0;
init_blk_pm: 	pm(__21160_anomaly_write_location)=r0;
#else
# if defined(__2126x__) && defined(__WORKAROUND_2126X_ANOMALY4__)
init_blk_pm:				PM(I9,M14)=PX; nop;
# else
init_blk_pm:				PM(I9,M14)=PX;
# endif
#endif
blk_inits_pm:			NOP;

finish_inits:		RTS;			/*Just return for now*/

/* IMPORTANT NOTE: The cache MUST be cleared before ANY PMDA accesses are made! */
___lib_setup_hardware:
#if !defined(__ADSP21020__)
			CALL (PC, ___lib_clear_cache);
#endif
			CALL (PC, ___lib_clear_irptl);
			RTS (DB);
			pm_1=1;
			pm_lnt=0;

.___lib_setup_hardware.end:
.___lib_setup_processor.end:
.ENDSEG;