/******************************************************************************** * * Embedded Studio (C) 2007 * * File: ES_FRAM.h * Desc: Ramtron FRAM Driver Functions * CPU: Analog Device ADSP-21369 * Slave Device: Ramtron FM25CL64 * **********************************************************************************/ #ifndef __ES_FRAM_H__ #define __ES_FRAM_H__ /********************************************************************************* FM25CL64 Op-code commands **********************************************************************************/ #define FRAM_WREN 0x06 //set write enable latch #define FRAM_WRDI 0x04 //write disable #define FRAM_RDSR 0x05 //read status register #define FRAM_WRSR 0x01 //write status register #define FRAM_READ 0x03 //read memory data #define FRAM_WRITE 0x02 //write memory data #define FARM_INIT_STATUS 0x80 //status initial set value #define FRAM_START_ADDR 0x0 //FRAM start address /********************************************************************************* ADSP-21269 SPI Baud Rate = Peripheral Clock Rate /(4)x(BAUDR) assume the peripheral clock is 160 MHz **********************************************************************************/ #define FRAM_BAUD_RATE_DIVISOR 2 //160 MHz / 4x2 = 20 MHz /********************************************************************************* SPI Registers **********************************************************************************/ typedef union st_spictl // SPI Control Registers (SPICTL, SPICTLB) { int ALL; // all 32 bits struct { int H :16; int L :16; } WORD; struct { int RSRVD0 :11; // bit[31:21], reserved int ILPBK :1; // bit[20], Internal Loop Back int RXFLSH :1; // bit[19], Clear RXSPI int TXFLSH :1; // bit[18], Flush Transmit Buffer int SMLS :1; // bit[17], Seamless Transfer int SGN :1; // bit[16], Sign Extend int PACKEN :1; // bit[15], PACKEN int SPIEN :1; // bit[14], SPI Port Enable int OPD :1; // bit[13], Open Drain Output Enable int SPIMS :1; // bit[12], SPI Master Select int CLKPL :1; // bit[11], Clock Polarity int CPHASE :1; // bit[10], Clock Phase int MSBF :1; // bit[9], Most Significant Byte First int WL :2; // bit[8:7], Word Length int RSRVD1 :1; // bit[6], reserved int DMISO :1; // bit[5], Disable MISO Pin int ISSEN :1; // bit[4], Input Slave-Select Enable int GM :1; // bit[3], When RXSPI is full, get data or discard incoming data int SENDZ :1; // bit[2], Send zero or the last word when TXSPI is empty int TIMOD :2; // bit[1:0], Transfer Initiation Mode } BIT; }ST_SPICTL; typedef union st_spibaud // SPIBAUD, SPIBAUDB Register { int ALL; // all 32 bits struct { int H :16; int L :16; } WORD; struct { int RSRVD1 :16; // bit[31:16], reserved int BAUD_DIVISOR :14; // bit[15:1], baud rate divisor int RSRVD0 :1; // bit[0], reserved } BIT; }ST_SPIBAUD; typedef union st_spiflg // SPI Port Flags Registers (SPIFLG, SPIFLGB) { int ALL; // all 32 bits struct { int RSRVD0 :20; // bit[31:12], reserved int SPIFLG3 :1; // bit[11], SPI Device Select Control int SPIFLG2 :1; // bit[10], SPI Device Select Control int SPIFLG1 :1; // bit[9], SPI Device Select Control int SPIFLG0 :1; // bit[8], SPI Device Select Control int ISSS :1; // bit[7], Input Service Select int RSRVD1 :3; // bit[6:4], reserved int DS3EN :1; // bit[3], SPI Device Select Enable int DS2EN :1; // bit[2], SPI Device Select Enable int DS1EN :1; // bit[1], SPI Device Select Enable int DS0EN :1; // bit[0], SPI Device Select Enable } BIT; }ST_SPIFLG; typedef union st_spistat // SPI Port Status (SPISTAT, SPISTATB) Registers { int ALL; // all 32 bits struct { int RSRVD0 :24; // bit[31:8], reserved int SPIFE :1; // bit[7], External Transaction Complete int TXCOL :1; // bit[6], Transmit Collision Error int RXS :1; // bit[5], Receive Data Buffer Status int ROVF :1; // bit[4], Reception Error int TXS :1; // bit[3], Transmit Data Buffer Status int TUNF :1; // bit[2], Transmission Error int MME :1; // bit[1], Multimaster Error or Mode-Fault Error int SPIF :1; // bit[0], SPI Transmit or Receive Transfer Complete } BIT; }ST_SPISTAT; typedef union st_spidmac // SPI DMA Configuration Registers (SPIDMAC, SPIDMACB) { UINT32 ALL; // all 32 bits struct { int H :16; int L :16; } WORD; struct { int RSRVD0 :15; // bit[31:17], reserved int SPICHS :1; // bit[16], DMA Chain Loading Status int SPIDMAS :1; // bit[15], DMA Transfer Status int SPIERRS :1; // bit[14], DMA Error Status int SPISx :2; // bit[13:12], DMA FIFO Status int SPIMME :1; // bit[11], Multimaster Error int SPIUNF :1; // bit[10], Transmit Underflow Error (SPIRCV = 0) int SPIOVF :1; // bit[9], Receive OverFlow Error (SPIRCV = 1) int INTERR :1; // bit[8], Enable Interrupt on Error int FIFOFLSH :1; // bit[7], DMA FIFO Clear int RSRVD1 :2; // bit[6:5], reserved int SPICHEN :1; // bit[4], SPI DMA Chaining Enable int RSRVD2 :1; // bit[3], reserved int INTEN :1; // bit[2], Enable DMA Interrupt on Transfer int SPIRCV :1; // bit[1], DMA Write/Read int SPIDEN :1; // bit[0], DMA Enable } BIT; }ST_SPIDMAC; /********************************************************************************* SPI Register Address Mapping **********************************************************************************/ #define SPICTL (*(volatile ST_SPICTL *)0x1000) // SPI Control Register #define SPIFLG (*(volatile ST_SPIFLG *)0x1001) // SPI Flag register #define SPISTAT (*(volatile ST_SPISTAT *)0x1002) // SPI Status register #define TXSPI (*(volatile int *)0x1003) // SPI transmit data register #define RXSPI (*(volatile int *)0x1004) // SPI receive data register #define SPIBAUD (*(volatile ST_SPIBAUD *)0x1005) // SPI baud setup register #define RXSPI_SHADOW (*(volatile int *)0x1006) // SPI receive data shadow register #define IISPI (*(volatile int *)0x1080) // Internal memory DMA address #define IMSPI (*(volatile int *)0x1081) // Internal memory DMA access modifier #define CSPI (*(volatile int *)0x1082) // Contains number of DMA transfers remaining #define CPSPI (*(volatile int *)0x1083) // Points to next DMA parameters #define SPIDMAC (*(volatile ST_SPIDMAC *)0x1084) // SPI DMA control register /********************************************************************************* public function prototypes **********************************************************************************/ // Open a device bool NVM_FRAM_Open(void); // Close a device bool NVM_FRAM_Close(void); // Write to a device bool NVM_FRAM_Write( int ulStart, INT32 lCount, int *pData ); // Read from a device bool NVM_FRAM_Read( int ulStart, INT32 lCount, int *pData ); #endif //__ES_FRAM_H__