/*********************************************************************************
*
* Embedded Studio (C) 2007                                   
*                                                                                
* File: ES_SDRAM_Init.c
* Desc: SDRAM controller initialization for 16-bit SDRAM access
* CPU: Analog Device ADSP-21369
*
**********************************************************************************/


/*********************************************************************************
 * Function:  DSP_PLL_Init
 *
 * Desc: This function initializes PLL
 *
 * Params: None
 *
 * Returns: boolean
 *
 * Notes:   
 *		CLKIN= 20 MHz, Multiplier = 16, Divisor = 1, CCLK_SDCLK_RATIO 2.5
 *	   	Core clock = (20 MHz * 16) / 1 = 320 MHz
 *	   	SDRAM runs at 320 / 2.5 = 128 MHz
 *********************************************************************************/
bool DSP_PLL_Init(void)
{
	ST_PMCTL pmctl;

	pmctl.ALL = PMCTL.ALL;
	pmctl.BIT.INDIV = 0;		//input clk div = 1
	pmctl.BIT.PLLM = 16;		//PLL 16x
	pmctl.BIT.PLLD = 0;			//divided by 1	
	pmctl.BIT.DIVEN = 1;		//PLL Divider enable
	pmctl.BIT.SDCKR = 1;		//CCLK_SDCLK_RATIO 2.5
	pmctl.BIT.SDRAMOFF = 0;		//enable SDRAM
    pmctl.BIT.PLLBP = 1;		//enable PLL bypass mode
    
	PMCTL.ALL = pmctl.ALL;		//set PMCTL
	
    // Wait at least 4096 cycles for the pll to lock
    DSP_Delay (5000);
    
	PMCTL.BIT.PLLBP = 0;		//set PLL in normal mode
	
	return true;
}

/*********************************************************************************
 * Function:  DSP_SDRAM_Init
 *
 * Desc: This function initializes SDRAM control registers.
 *
 * Params: None
 *
 * Returns: boolean
 *
 * Notes:   
 *		RDIV = ((fSDCLK X t REF )/NRA) - (tRAS + tRP )
 *********************************************************************************/
bool DSP_SDRAM_Init(void)
{
	//set chip select
	ST_EPCTL epctl;
	epctl.ALL = 0;
    epctl.BIT.B0SD = 1;	//use MS0 for SDRAM chip select
	epctl.BIT.EPBR = 2;	//core has high priority
    EPCTL.ALL = epctl.ALL;
    
    //set refresh ratio count 
	ST_SDRRC sdrrc;
	sdrrc.ALL = 0;
    // (128*(10^6)*64*(10^-3)/4096) - (6+3) = 1991 = 0x7C7
	sdrrc.BIT.RDIV = 1991;	//refresh divisor
	sdrrc.BIT.SDMODIFY = 1;	//enable read optimization
	sdrrc.BIT.SDROPT = 1;
	SDRRC.ALL = sdrrc.ALL;

	//set SDRAM control register
    ST_SDCTL sdctl;
    sdctl.ALL = 0;
	sdctl.BIT.SDCL = 3;		//SDRAM CAS Latency = 3 cycles
	sdctl.BIT.DSDCTL = 0;	//enable SDRAM clock and signals
	sdctl.BIT.DSDCLK1 = 1;	//disable SDRAM clock 1
	sdctl.BIT.SDTRAS = 6;	//SDRAM tRAS Spec = 44 / 7.8 = 6 cycles
	sdctl.BIT.SDTRP = 3;		//SDRAM tRP Spec = 20 / 7.8 = 3
	sdctl.BIT.SDTRCD = 3;	//SDRAM tRCD Spec = 20 / 7.8 = 3 cycles.	
	sdctl.BIT.SDTWR = 2;		//SDRAM tWR Spec = (7.8 + 7.5) / 7.8 = 2 cycles.
	sdctl.BIT.SDPM = 0;		//power-up mode
	sdctl.BIT.SDCAW = 0;		//SDRAM Bank Column Address Width = 8 bits
	sdctl.BIT.SDRAW = 4;		//SDRAM Row Address Width = 12 bits
	sdctl.BIT.X16DE = 1;		//16 bit data bus width
	sdctl.BIT.SDBUF = 0;		//no buffer option
	sdctl.BIT.SDPSS = 1;		//start SDRAM power-up sequence on next memory access

	//choose self refresh mode
	sdctl.BIT.SDSRF = 1;		//enable self refresh
	sdctl.BIT.SDORF = 1;		//disable auto refresh

	SDCTL.ALL = sdctl.ALL;
	
	//dummy read to trigger power-up sequence
	int temp = *(INT32 *)0x200000;
	
	return true;
}