//********************************************************************************
*  Embedded Studio 2007                                   
*                                                                                
*  File: ES_UART.h
*  Desc: PC16550 UART Driver Functions
*
*********************************************************************************

#ifndef __ES_UART_H__
#define __ES_UART_H__

#define DR_BIT		0x0001
#define OE_BIT		0x0002
#define PE_BIT		0x0004

//int type is 32 bit in Analog Devices ADSP-21369

//UART16550 Register (IER)
typedef struct tUart16550IERStruct
{
	int RSRVD0		:28;	// bit[31:4], Reserved 
	int EDSSI		:1;		// bit[3], Enable MODEM Status Interrupt 
	int ELSI		:1;		// bit[2], Enable Receiver Line Status Interrupt 
	int ETBEI		:1;		// bit[1], Enable Transmitter Holding Reg Empty Interrupt  
	int ERBFI		:1;		// bit[0], Enable Received DATA Available Interrupt
} Uart16550IERStruct;

typedef union tUart16550IERUnion
{
    int ALL;
    Uart16550IERStruct BIT;
} Uart16550IERUnion;

//UART16550 Register (IIR)
typedef struct tUart16550IIRStruct
{
    int RSRVD0		:24;	// bit[31:9], reserved 
    int FIFOEN		:2;		// bit[7:6], FIFO's Enabled 
    int RSRVD1		:2;		// bit[5:4], Reserved 
    int IIB2		:3;		// bit[3:1], Interrtupt ID Bits 2-0 
    int IP			:1;		// bit[0], "0" if Interrupt Pending
} Uart16550IIRStruct;

typedef union tUart16550IIRUnion
{
    int ALL;
    Uart16550IIRStruct BIT;
} Uart16550IIRUnion;


//UART16550 Register (FCR)
typedef struct tUart16550FCRStruct
{
	int RSRVD0		:24;	// bit[31:8], reserved 
	int RCVRT		:2;		// bit[7:6], Receiver Trigger MSB 
	int RSRVD1		:2;		// bit[5:4], Reserved 
	int DMA_MS		:1;		// bit[3], DMA Mode Select 
	int XMIT_FIFOR	:1;		// bit[2], Transmit FIFO Reset 
	int RCVR_FIFOR	:1;		// bit[1], Receiver FIFO Reset 
	int FIFOE		:1;		// bit[0], FIFO Enable 
} Uart16550FCRStruct;

typedef union tUart16550FCRUnion
{
    int ALL;
    Uart16550FCRStruct BIT;
} Uart16550FCRUnion;

//UART16550 Register (LCR)
typedef struct tUart16550LCRStruct
{
	int RSRVD		:24;	// bit[31:8], reserved 
	int DLAB		:1;		// bit[7], Divisor Latch Access Bit 
	int SB			:1;		// bit[6], Set Break 
	int SP			:1;		// bit[5], Stick Parity 
	int EPS			:1;		// bit[4], Even Parity Select 
	int PEN			:1;		// bit[3], Parity Enable 
	int STB			:1;		// bit[2], Number of Stop Bits 
	int WLS			:2;		// bit[1:0], Word Length Select Bits 1-0 
} Uart16550LCRStruct;

typedef union tUart16550LCRUnion
{
    int ALL;
    Uart16550LCRStruct BIT;
} Uart16550LCRUnion;

//UART16550 Register (MCR)
typedef struct tUart16550MCRStruct
{
	int RSRVD0		:27;	// bit[31:5], Reserved 
	int LOOP		:1;		// bit[4], LOOP 
	int OUT2		:1;		// bit[3], Out2 
	int OUT1		:1;		// bit[2], Out1 
	int RTS			:1;		// bit[1], Request To Send 
	int DTR			:1;		// bit[0], Data Terminal Ready 
} Uart16550MCRStruct;

typedef union tUart16550MCRUnion
{
    int ALL;
    Uart16550MCRStruct BIT;
} Uart16550MCRUnion;

//UART16550 Register (LSR)
typedef struct tUart16550LSRStruct
{
	int RSRVD0		:24;	// bit[31:8], Reserved 
	int ERF			:1;		// bit[7], Error In Receiver FIFO 
	int TEMT		:1;		// bit[6], Transmitter Empty 
	int THRE		:1;		// bit[5], Transmitter Holding Register 
	int BI			:1;		// bit[4], Break Interrupt 
	int FE			:1;		// bit[3], Framing Error 
	int PE			:1;		// bit[2], Parity Error 
	int OE			:1;		// bit[1], Overrun Error 
	int DR			:1;		// bit[0], Data Ready 
} Uart16550LSRStruct;

typedef union tUart16550LSRUnion
{
    int ALL;
    Uart16550LSRStruct BIT;
} Uart16550LSRUnion;

//UART16550 Register (MSR)
typedef struct tUart16550MSRStruct
{
	int RSRVD0		:24;	// bit[31:8], Reserved 
	int DCD			:1;		// bit[7], Data Carrier Detect 
	int RI			:1;		// bit[6], Ring Indicator 
	int DSR			:1;		// bit[5], Data Set Ready 
	int CTS			:1;		// bit[4], Clear To Send 
	int DDCD		:1;		// bit[3], Delta Data Carrier Detect 
	int TERI		:1;		// bit[2], Trailing Edge Ring Indicator 
	int DDSR		:1;		// bit[1], Delta Data Set Ready 
	int DCTS		:1;		// bit[0], Delta Clear To Send 
} Uart16550MSRStruct;

typedef union tUart16550MSRUnion
{
    int ALL;
    Uart16550MSRStruct BIT;
} Uart16550MSRUnion;

//parity enum
typedef enum tParityEnum
{
    NONE = 0,    	//No parity check occurs.
    ODD,    		//Sets the parity bit so that the count of bits set is an odd number.
    EVEN    		//Sets the parity bit so that the count of bits set is an even number.
} ParityEnum;

//word length enum
typedef enum tWordLength
{
    WL_5 = 0,    	//00 - 5 bits
    WL_6,    		//01 - 6 bits
    WL_7,    		//10 - 7 bits
	WL_8			//11 - 8 bits
} WordLengthEnum;

//stop bits enum
typedef enum tStopBits
{
    SB_1 = 0,    	//0 - 1 stop bit
	SB_2			//1 - 2 stop bits
} StopBitsEnum;

//UART configuration struct
typedef struct tUartConfigStruct
{
    UINT16 BaudRate;			//baud rate
    WordLengthEnum DataBits;	//byte width
    bool Sticky;				//sticky bit
    ParityEnum Parity;			//parity
    StopBitsEnum StopBits;		//stop bits
    UINT16 RxFifoLevel;			//Receiver FIFO trigger level
} UartConfigStruct;

//FPGA UART control block
typedef struct tFpgaUartCtrlStruct
{
    volatile int *RBR;					//receiver buffer register (read only)
    volatile int *THR;					//transmit holding register (read only)
    volatile int *DLL;					//divisor latch (LS)
    volatile int *DLM;					//divisor latch (MS)
    volatile Uart16550IERUnion *IER;	//interrupt enable register
    volatile Uart16550IIRUnion *IIR;	//interrupt identifier register (read only)
    volatile Uart16550FCRUnion *FCR;	//FIFO control register (write only)
    volatile Uart16550LCRUnion *LCR;	//line control register
    volatile Uart16550MCRUnion *MCR;	//modem control register
    volatile Uart16550LSRUnion *LSR;	//line status register
    volatile Uart16550MSRUnion *MSR;	//modem status register
    volatile int *SCR;					//scratch register
} FpgaUartCtrlStruct;

typedef enum tFIFOTriggerLevel
{
    TRIGGER_LEVEL_01,	//1 byte
    TRIGGER_LEVEL_04,	//4 bytes
    TRIGGER_LEVEL_08,	//8 bytes
    TRIGGER_LEVEL_14,	//14 bytes
} FIFOTriggerLevel;

//IIR bit[3:1] defines the type of interrupt
typedef enum tIIRIntType
{
    IIR_MODEM,			//0, modem error
    IIR_THRE,			//1, Transmitter Holding Register Empty
    IIR_RX_DATA_READY,	//2, Receiver data available
    IIR_RX_LINE_ERR,	//3, Rx line error (OE, PE, FE, BI)
    IIR_UNDEFINED1,		//4, undefined
    IIR_UNDEFINED2,		//5, undefined
    IIR_CHAR_TIMEOUT	//6, Character Timeout
} IIRIntType;

//public functions
bool FPGA_UART_Open(int ch, FpgaUartCtrlStruct *pUart, UartConfigStruct *pConfig);
int FPGA_UART_Read(FpgaUartCtrlStruct *pUart, int *pBuffer, int nBytes, int mark);
int FPGA_UART_Write(FpgaUartCtrlStruct *pUart, int *pBuffer, int nBytes);
bool FPGA_UART_Close(FpgaUartCtrlStruct *pUart);

#endif	//__ES_UART_H__