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TI TMS320F28xx On-Chip RAM Integrity Test

;********************************************************************************
;* (C) 2007 Embedded Studio, All rights reserved.
;*
;* Description: TI TMS320C28xx RAM self test routine
;*
;********************************************************************************

;********************************************************************************
;* All RAM sector start address and size definition
;********************************************************************************
        .global _RamSectors
        .sect ".const"
        .align 2


_RamSectors:
        .field 0x40, 32                                    ;RAM M0
        .field 0x3C0, 16                                  ;M0 length excluding vector
        .space 16
        .field 0x400, 32                                  ;RAM M1
        .field 1024, 16                                    ;M1 length
        .space 16
        .field 0xD00, 32                                  ;PIE vector RAM
        .field 256, 16                                      ;PIE Vector RAM length
        .space 16
        .field 0x8000, 32                                 ;RAM L0
        .field 4096, 16                                     ;L0 length
        .space 16
        .field 0x9000, 32                                 ;RAM L1
        .field 4096, 16                                     ;L1 length
        .space 16
        .field 0x3F8000, 32                             ;RAM H0
        .field 8192, 16                                    ;H0 length
        .space 16

;**********************************************************************************
;* Function: _RamIntegrityTest
;*
;* Description:
;*       This function tests all sectors of on-chip RAM set in RamSectors
;*
;* Return:
;*       TRUE if all RAM locations were verified correctly;
;*       FALSE if any of the RAM location was tested to be incorrect.
;*
;**********************************************************************************

        .def _RamIntegrityTest

        .sect ".text"
        .global _RamIntegrityTest

_RamIntegrityTest:
        EALLOW                       ;this instruction is needed only
                                             ;because PIE Vector RAM is EALLOW protected
        ADDB SP, #2
        MOV *-SP[2], #6
        MOV *-SP[1], #0
        MOV AL, *-SP[2]
        CMP AL, *-SP[1]
        B L3, LEQ
L1:
        SETC SXM
        MOVL XAR4, #_RamSectors
        MOV ACC, *-SP[1] << 2
        ADDL XAR4, ACC
        MOVL XAR5, #_RamSectors+2
        MOV ACC, *-SP[1] << 2
        ADDL XAR5, ACC
        MOVL XAR4, *+XAR4[0]
        MOV AL, *+XAR5[0]
        LCR #_RamSectorTest
        CMPB AL, #0
        BF L2, NEQ
        MOVB AL, #0
        B L4, UNC
L2:
        INC *-SP[1]
        MOV AL, *-SP[2]
        CMP AL, *-SP[1]
        B L1, GT
L3:
        MOVB AL, #1
L4:
        SUBB SP, #2
        EDIS
        LRETR

;**********************************************************************************
;* Function: _RamSectorTest
;*
;* Description:
;*       This function tests one sector of on-chip RAM set in RamSectors
;*
;* Params:
;*       RAM sector start address and length
;*
;* Return:
;*       Boolean, TRUE if all RAM locations were verified correctly;
;*       FALSE if any of the RAM location was tested to be incorrect.
;*
;*********************************************************************************
        .sect ".text"
        .global _RamSectorTest

_RamSectorTest:
        ADDB SP, #4
        MOV *-SP[3], AL
        MOVL *-SP[2], XAR4
        MOV *-SP[4], #0
        MOV AL, *-SP[3]
        CMP AL, *-SP[4]
        B L8, LOS
L5:
        MOVL XAR6, *-SP[2]
        SETC SXM
        MOV ACC, *-SP[4]
        ADDL ACC, XAR6
        MOVL XAR4, ACC
        MOV *+XAR4[0], #0x5555                 ;writes first pattern
        MOVL XAR6, *-SP[2]
        MOV ACC, *-SP[4]
        ADDL ACC, XAR6
        MOVL XAR4, ACC
        CMP *+XAR4[0], #0x5555                 ;reads back and compares
        BF L6,EQ
        MOVB AL,#0
        B L9,UNC
L6:
        MOVL XAR6, *-SP[2]
        MOV ACC, *-SP[4]
        ADDL ACC, XAR6
        MOVL XAR4, ACC
        MOV *+XAR4[0], #0xAAAA               ;writes second pattern
        MOVL XAR6, *-SP[2]
        MOV ACC, *-SP[4]
        ADDL ACC, XAR6
        MOVL XAR4, ACC
        CMP *+XAR4[0], #0xAAAA               ;reads back and compares
        BF L7, EQ
        MOVB AL, #0
        B L9, UNC
L7:
        INC *-SP[4]
        MOV AL, *-SP[3]
        CMP AL, *-SP[4]
        B L5, HI
L8:
        MOVB AL, #1
L9:
        SUBB SP, #4
        LRETR

; End of file